1. Functions of IA-32E mode

The IA-32E mode is the third of the two modes that the CPU operates in — real mode and protected mode. One of the main differences is the number of bits the CPU runs. In real mode, the valid length of the CPU register is 16 bits. In protected mode, the valid length of the CPU register is 32 bits. In IA-32E mode, the CPU register length is 64 bits. Why add IA-32E mode after protected mode? Since the register is 32 bits long in protected mode, the CPU’s maximum addressing range is 232=4294967296Byte2^{32}=4294967296Byte, or 4294967296Byte. Memory is now larger than 4GB, so a larger number of addressing bits is needed to help the CPU find the address in memory. In ia-32e mode, the addressing range is theoretically up to 264Byte2^{64} byte 264, or 17179869184GB.

2. Ia-32e mode of addressing

The IA-32E mode of addressing is the same as the protected mode of addressing in the first half, while the ia-32E mode forces page table addressing in the second half. So the difference between them is that IA-32E mode continues to use page table addressing after using protected mode addressing.

The first half of the address is the same as in protected mode, except that the physical address obtained in protected mode is Canonical linear, instead of physical, in IA-32E mode, and will be converted to a physical address based on the page table.

2.1 Page table address translation

The figure is obtained by means of segment selectorsCanonical linear addressAfter, also need to go through the page table conversion. The first step in converting a page table address is to convert fromCr3 control registerLooking for toPML4That’s the base address of the level 4 page table, and then through 64 bitsCanonical linear addressThe offset from bit 47 to 39 is obtained, and the page entry in the page table is selected by the offset. By the contents of the page table entryPDPTThe base address of the third level page table, and the page entry in the page table is selected by a 38-30 bit offset. Repeat this four times to get the physical address page address, and finally add 12-0 bits of in-page offset to get the physical address.

2.2 CR3 control register

Where PWT and PCD are used to determine memory access PML4 mode, set to 0. And since the minimum size of the page table is 4KB, the physical address of the PML4 page table needs to be multiplied by 4096, that is to say, the data in the CR3 control register is the physical address of the PML4 page table.

2.3 PML4 page table

Unlike the CR3 control register, the last three digits of the PML4 page entry should be all 1s, and the last three digits should be 0x007 in hexadecimal notation. That is, if the physical base address of the PDPT page table is 0x92000, then the contents of the PML4 page entry should be 0x92007

2.4 PDPT page table

After arriving from the PML4 page table to the PDPT page table, PDPT page table entries are different from PML4. PDPT page table entries have two forms, depending on whether bit 7 is 1 or 0. If bit 7 is 0, the page table conversion needs to proceed to the next PDT page table. If bit 7 is 1, then the page table transformation takes the 1GB physical page directly from bit 30 with the current page entry, plus the offset 30 bits earlier to get the physical address directly. That is, if we need to use 1GB physical pages, the page table entry placed in the PDPT should end in 0x087, and if we need smaller physical pages, it should end in 0x007.

2.5 PDT page table

Like the PDPT page table, the PDT page table has two forms, again depending on bit 7. If bit 7 is 0, the page table conversion still needs to proceed to the next PT page table; If bit 7 is 1, the page table conversion takes the current page entry from bit 22 onwards to the 2MB physical page, plus the offset before 22 bits to get the physical address directly. Similarly, if we need to use 2MB physical pages, the page table entry placed in the PDT should end in 0x087, and if we need smaller physical pages, we should end in 0x007.

2.6 PT page table

The last page table, PT, is 4KB in size, so it has only one form, which must be 0x007 up to 11 bits, and the base address of the 4KB physical page after 11 bits.

3. Page table addressing instance

Suppose we now set up the following data structure for the page table

; === PML4页表 mov dword[0x90000], 0x91007; === PDPT page table mov dword[0x91000], 0x92007; === PDT page table mov dword[0x92000], 0x93007; === PT table mov dword[0x93000], 0x007; Item 0 mov dword[0x93008], 0x1007; Item 1, each item size 64 bits, i.e. 8 bytes mov dWORD [0x93038], 0x7007; Item 7, total 7*8=56 bytes, hex 56=10 base 38; Mov eAX, 0x90000 mov cr3, EACopy the code

Then the addressing mode is