The Makefile an overview

What is in the Makefile?

Makefiles contain five main things: explicit rules, implicit rules, variable definitions, file directives, and comments.

  1. Explicit rules. Explicit rules specify how to generate one or more object files. This is the command generated by the writer of the Makefile that clearly indicates the file to be generated, the file’s dependencies on the file.
  2. Implicit rule. Since our make has automatic derivation, the implicit rules allow us to write makefiles crudely and briefly, which is supported by make.
  3. Definition of a variable. In a Makefile we define a series of variables, which are usually strings. This is a bit like C macros. When the Makefile is executed, the variables are extended to the corresponding reference location.
  4. File instructions. It consists of three parts. One refers to another Makefile in a Makefile, just like include in C. The other is to specify the valid part of a Makefile depending on the situation, like precompiling #if in C. Another is to define a multi-line command. I will talk about this in a later part.
  5. The comments. The Makefile has only one line of comment. Like UNIX Shell scripts, it is commented with the “#” character, which is like the “//” in C/C++. If you want to use a “#” character in your Makefile, you can escape it with a backslash, such as “/#”.
  6. Finally, it is worth mentioning that commands in makefiles must start with the [Tab] key.

The file name of the Makefile

By default, the make command looks for files named “GNUmakefile”, “makefile”, “makefile” in the current directory in order, and finds the explain file. Of the three filenames, it is best to use the name “Makefile” because the first character of the file name is uppercase, which gives it a more visible feel. It is best not to use “GNUmakefile”, which is recognized by GNUmake. There are other makes that are only sensitive to all-lowercase “makefile” filenames, but basically, most of them support both “makefile” and “makefile” filenames by default.

Of course, you can write makefiles with other names, such as “make. Linux”, “make. Solaris”, “make. AIX”, etc. If you want to specify a specific Makefile, you can use the “-f” and “–file” arguments of Make, such as: Make -f make.Linux or make –file make.

3. Reference other makefiles

Use the include keyword in a Makefile to include other makefiles, much like C’s #include. The included file is placed exactly where it was included in the current file. The syntax for include is:

include <filename>
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Filename can be the file mode of the current operating system Shell (path and wildcard can be preserved)

Include can be preceded by blank characters, but it should never start with the [Tab] key. Include and

can be separated by one or more Spaces. For example, if you have several makefiles: a.mk, b.mk, c.mk, a file called foo.make, and a variable $(bar) that contains e.mk and f.mk, then the following statement:

include foo.make *.mk $(bar)
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Is equivalent to

include foo.make a.mk b.mk c.mk e.mk f.mk
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The make command begins by finding the other makefiles indicated by include and placing their contents in the current location. Like the #include directive in C/C++. If no absolute or relative path is specified for the file, make will first look in the current directory. If not, make will also look in the following directories:

  1. If make executes with the “-i” or “–include-dir” argument, then make looks in the directory specified by that argument.
  2. If the directory<prefix>/include/usr/local/bin /usr/include /usr/local/bin /usr/include

If a file isn’t found, make generates a warning, but it doesn’t immediately produce a fatal error. It continues to load other files, and once it has finished reading the Makefile, make retries the files that were not found or cannot be read. If it still fails, make will display a fatal message. If you want make to ignore unreadable files and continue execution, you can add a minus sign “-” before include. Such as:

-include <filename>
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This means that no matter what errors occur in the include process, do not report an error and continue execution. A related command compatible with other versions of make is sinclude, which does the same thing.

Environment variables MAKEFILES

If you have an environment variable MAKEFILES defined in your current environment, make will do an include-like action with the value in the variable. The values in this variable are other makefiles, separated by Spaces. Unlike include, however, the “target” of the Makefile introduced from this environment variable does not take effect, and make ignores errors in the files defined in the environment variable.

However, I recommend not using this environment variable here, because as soon as this variable is defined, all makefiles will be affected by it when you use make, which is not what you want. Just for the record, if something weird happens to your Makefile, check to see if this variable is defined in your current environment.

How does make work

GNU make works by performing the following steps:

  1. Read all the makefiles.
  2. Read other makefiles to be included.
  3. Initialize a variable in a file.
  4. Derive implicit rules and analyze all rules.
  5. Create dependency chains for all object files.
  6. Based on the dependencies, decide which targets to regenerate.
  7. Execute the build command.

Steps 1-5 are the first stage, and steps 6-7 are the second. In the first phase, if the defined variable is used, make expands it to the used position. However, make does not completely expand immediately. Make uses a delaying tactic. If a variable appears in a dependency rule, it will only expand inside the dependency if the dependency is decided to be used.

Of course, you don’t have to know how this works, but knowing it will make you more familiar with it. With this foundation, the rest is easy to follow.

The original connection: blog.csdn.net/haoel/artic…