directory

1. Introduction to Computer systems 2. Data Representation 3. Operation methods and Arithmetic Units 4

  1. Von Neumann computer composition

Host (CPU + memory), peripherals (input device + output device + external memory), bus (address bus + data bus + control bus) 2. Computer hierarchy

Application – High-level Language – Assembly Language – Operating System – Instruction set Architecture Layer – Microcode Layer – Hardware logic layer 3. Computer performance index

Non-time indicator [word length] The number of bits that a machine can process at a time, usually 32 or 64 bits. Generally refers to the number of the data bus between the computer and the memory [main memory capacity] the size of main memory [storage bandwidth] the number of binary bits exchanged with main memory per unit time B/s time indicator [main frequency F] the frequency of clock oscillation Hz; [Clock cycle T] time when the clock oscillates once T [external frequency] The clock frequency synchronized between the CPU and the mainboard, and the working frequency of the system bus; Multiple of main frequency and external frequency = main frequency/external frequency [CPI] clock cycles per instruction, the number of cycles required to execute an instruction (average) Total number of instructions executed per second MIPS= F/CPI (ignore unit

  1. The basic concept

[x] original =0101 2. Several machine numbers

X = -0101, [x] x = -0101, [x] x = -0101, [x] x = -0101, [x] x = 2^n + x = 0011 PS: Here talk about to complement code and move code own understanding. Complement is to subtraction for addition convenient computer design operation, shift code is to facilitate the comparison of size, used in the order of floating point numbers.

Complement – In any modular system, subtraction can be represented by adding its complement. The simplest example would be a clock with module 12. For example, if it’s 3 o ‘clock, then minus 5 hours is equal to plus 7 hours, which is 10 o ‘clock. So 7 is the complement of 5.

Frameshift – data correspondence moves one position at a time so that seemingly small numbers are actually small. For example, 0000 used to be 0, now it’s -128, then 0001 is -127, all the way up to 1111 is +127, so it’s easy to compare.

  1. Fixed point and floating point numbers

Fixed point number: the decimal point is fixed x. XXXXX, indicating limited range, forget it

Floating point: The range and precision of a number are expressed separately.

Common format: EEEE…… EMMM……. M, E part is the order code (number range I), M part is the mantissa (number precision). Disadvantages: rank code and mantissa digit is not fixed, too flexible

IEEE754 format: Recite after me —-

32-bit is (single precision) : 1 bit sign bit S + 8 bit offset index E + 23 bit effective mantissa M, offset value 127.

64-bit is (double precision) : 1 sign bit S + 11 offset exponent E + 52 effective mantissa M, offset value 1023.

The truth value is (for example, 32 bits) N = (-1)^S * 2^(e-127) * 1.m

Special cases of floating point numbers:

E=0,M=0: machine zero

E=255,M=0: infinity, corresponding to x/0

E=255,M! =0: non-numeric NaN, which corresponds to 0/0

  1. Data validation

Basic principle: add redundant code spacing: the minimum code spacing of different binary bits between legal codes and error detection and correction ability: code spacing D >= E +1: check e error spacing D >= 2T +1: correct T error spacing D >= E + T +1: check E error and correct T error. (e>=t) PS: Here is my understanding, increasing the code distance means increasing the number of illegal codes. If you see the illegal codes, you can check the error, while if you see the legal codes in the illegal code distance, you can think what is correct (simple understanding, please refer to the figure below), that is, you can correct the error. I’ve seen a good geometry diagram here. Savor it:

For example, if there are 8 bits in total and the code spacing is 1, no errors will be detected because all codes are legal. If the code spacing is 2, then the legal code should look like 0000000000000011 0000110000001111, then if there is an illegal code like 00000001, then the error can be checked, but if both of them are wrong, then it may jump to another legal code. I can’t check for two.

So if the code size is 3, then the legal code should look like 00000000,00000111,00111000,00111111, so if there’s one bit error 00000001, or two bits of error 00000011, both of them are illegal codes and can be checked for errors. In this case, you can correct 00000001 to 00000000 and 00000011 to 00000111. But if three of them are wrong at the same time, you can’t check them.

Common check policies: parity check, CRC check, hamming check

Ps: Haiming coding the strongest video demo tutorial: www.youtube.com/watch?v=373…

Three, operation method and arithmetic unit

  1. Fixed-point number operation and overflow

Fixed-point number addition and subtraction: subtracting adds directly with the complement, ignoring the carry

Overflow: The result of an operation goes beyond the representation of a data type

Overflow detection method: the unified idea is that positive and negative get negative or negative get regular overflow, and positive and negative can’t overflow

Method 1: V = XYS + XYS (XY is the sign bit of the two addends, S is the sign bit of the result, and _ is not), then V = 1 is overflow

Method 2: V = C0 ⊕ C1 (C0 is the carry of the highest data bit and C1 is the carry of the sign bit), then V = 1 is overflow

Method 3: V = Xf1 ⊕ Xf2 (data using variant complement Xf1Xf2 X0X1X2X3…)

PS: The above methods are all based on the starting point of the circuit design of positive and negative and negative and regular overflow

  1. Complement one – digit multiplication – Booth algorithm

[x·y] complement = [x] complement ·(-y0+∑ yi2-i)

= [x] = [x] = [x] = [x] = [x] = [x] = [x] = [x]

Fill = [x], [y0 + (y1 – y12-1) + (- y22 y22-1-2) +… + (yn2 – (n – 1) – yn2 – n)]

Fill = [x], [(y1 – y0) + (y2 – y1) 2-1 +… + (yn – yn – 1) 2 – (n – 1) + (0 – yn) 2 – n]

To sum up, the rules for designing digital circuits are:

If it is 0 or 11, move it right one bit to 01 and add the complement of x, and then move it right one bit to 10 and add the complement of -x and then move it right one bit. There are two reasons:

1) If there is a 0 in binary, the operation can not be performed

2) If there are consecutive 1’s, the calculation times can be reduced, for example, a * 001111100 = A * (010000000-0000000100)

So every time you say yn+1 – yn, you can reduce the number of calculations

Reference: www.cnblogs.com/xisheng/p/9…

  1. Fixed point number division — omitted, did not find good information

  2. Floating-point addition and subtraction

(1) Find the order difference, and align the small order with the large one

(2) Mantissa addition and subtraction

(3) Normalization of results

Storage system

  1. Storage system hierarchy

The main memory speed is slow because the main memory growth is not synchronized with the CPU, and the main memory is accessed repeatedly during the execution of commands

Causes of insufficient main storage capacity:

There are technical factors restricting the main memory capacity: for example, the main memory capacity is defined by related technical specifications such as cpus and motherboards. The main memory capacity requirements for applications are increasing: window98-8 m, Windows 8-1G —–> storage system structure layers: CPU — Cache1 — Cache2 (resolve speed) — Main memory — Auxiliary memory (resolve capacity)

Theoretical basis of Storage System structural Hierarchy:

Temporal locality: programs are represented as circular structures Spatial locality: programs are represented as sequential structures 2. Organization of data in main memory

Memory word length: The number of binary digits contained in a storage unit of main memory, which on most computers is addressed in bytes and consists mainly of 32 and 64 bits

The relationship between data stores and boundaries:

Aligned according to the boundary of data storage, not aligned according to the data storage alignment border relationship with the store address: (32 bits long, for example) double word boundary alignment: the starting address the bottom three to 000 (8 bytes integer times) words long boundary alignment: at the end of the starting address two of 00 integer times (4 bytes) half word long boundary alignment: Start address last bit is 0 (integer multiple of 2 bytes) Big-endian and small-endian storage:

Big end: The highest byte address is the data address (0123 is saved as 0123) Small end: the lowest byte address is the data address (0123 is saved as 3210) 3. Memory classification

SRAM memory: fast access, but low integration, large power consumption, do cache DRAM memory: slow access, but high integration, low power consumption, main memory DRAM refresh mode: centralized refresh, scattered refresh, asynchronous refresh

  1. Expansion of main storage capacity

Bit expansion method: 8K x 8 bits > 8K x 32 bits Word expansion method: 8K x 8 bits > 32K x 8 bits Simultaneous expansion method: 8K x 8 bits > 32K x 32 bits 5. Basic principles of Cache

Data: THE CPU and cache exchange words, and the cache and memory exchange blocks Read: Hit, miss Write: Write through policy, write back policy Write Policy Write Through policy: Writes data to the cache and memory at the same time as if it were writing through the cache. If the data is not matched, the data is written to main storage first and optionally allocated to the cache at the same time (write allocation/non-write allocation). Write back Policy: The data is written to the cache and is handled only when the cached data is replaced back to main storage. Dirty bits are required. As if written back to main memory after an interval, the address mapping mechanism is linked to memory: Address = block address + internal offset address = (Tag + Index) + internal offset address Each line has the same size as the main memory block. Each line = TAG + Data + Valid + Dirty The three mapping modes are all associated: Cache line number = RANDOM (memory block number) Direct association: Cache line number = memory block number % Number of cache lines Group association: the two mapping modes are combined. 8 lines 1 way group association is full association, 8 lines 8 way group association is direct association replacement algorithm first-in, first-out method -FIFO recently least frequently used method -LFU recently least used method -LRU random replacement method

  1. Virtual memory

Problem solved: Insufficient main storage capacity. The Memory Management Unit (MMU) + the page table + TLB (Transaction Lookaside Buffer) Page translation process: Virtual address = Virtual page number + Intra-page offset ==> Physical page number + intra-page offset 7. RAID

Concept: Redundant Arrays Independent Disks that use xOR operations to recover data (X ⊕ Y = Z -> X = Y ⊕ Z) Evenly distributed with stripes Disk 0 Disk 1 Disk 2 Disk 3 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 RAID1: mirroring redundancy Disk 0 Disk 1 D0 D0 D1 D1 D2 D2 RAID3/4: Check disk 0 Disk 1 Disk 2 Check disk D0 D1 D2 P0 D3 D4 D5 P1 D6 D7 D8 P2 RAID5: Parity information Distributed disk 0 Disk 1 Disk 2 Disk 3 D0 D1 D2 P0 D3 D4 P1 P5 D6 P2 D7 D8 P3 D9 D10 D11 RAID10/01:10 Yes Mirroring and then striping, 01 Yes striping and then mirroring RAID50: First RAID5, then striping 5, command system

  1. Basic concepts of instruction system

Instruction set: A collection of all the instructions of a machine. Series of machines (produced by the same company in different periods); Compatibles (produced by different companies) Instruction word length: the number of bits contained in the instruction, including equal length instruction and variable length instruction. Instruction classification according to hierarchy: advanced, assembly, machine, microinstruction according to address code Number of fields: zero, one, two, three Address instruction according to operands physical location memory-storage (SS) register-register (RR) register-storage (RS) According to instruction function: Transmission, arithmetic operation, bit operation, control transfer instruction format: opcode + data source + addressing mode

  1. Addressing mode

Instruction addressing: sequential addressing, jump addressing operand addressing: immediate number addressing: address code field is the operand itself MOV AX, 200H Register addressing: address code field is the register address MOV AX, BX direct addressing: MOV AX, [BX] MOV AX, [BX] MOV AX, [BX] MOV AX, [BX] MOV AX, [BX] MOV AX, [BX] MOV AX, [BX] MOV AX, [BX] MOV AX, [BX] MOV AX, [BX] MOV AX, [BX] MOV AX, [BX] MOV AX, 32[B] address: MOV AX, 32[SI] 3. MIPS

Three instruction formats

R-type instructions: 6bits 5bits 5bits 5bits 5bits 6bits 000000 Rs Rt Rd Shamt funct

Type I instruction: 6bits 5bits 5bits 16bits OP Rs Rt Immediate number

Type J instruction: 6bits 26bits OP Instant number six, central processing unit

  1. CPU components and functions

  2. Data path

Abstract model: Clock-driven, A –> Combined logic –> B D trigger timing model: Stable for A period of Time before triggering: Setup Time: stable for A period of Time after triggering: Hold Time The Time when the clock is triggered until the output is stable: the relationship between the trigger delay (Clk_to_Q) and the clock cycle: Clock period > Clk_to_Q + critical path latency + Setup Time Clk_to_Q + Shortest path latency > Hold Time 3. Instruction cycle

The general flow of instruction execution

Basic Concepts Clock cycle = beat pulse = oscillation cycle Machine cycle = CPU cycle = Minimum time to read an instruction from main memory Instruction cycle = Time to read an instruction from main memory and execute an instruction

Instruction time control: number of machine cycles Number of beats Synchronization mode Practice Constant instruction period by machine period MIPS Single period Variable Instruction period by clock period MIPS multiple periods

  1. CPU design

Seven, bus

  1. The characteristics and application of system bus

Bus concept: connect the components of a computer system

Bus categories :(external/internal, system/non-system, serial/parallel, synchronous/asynchronous…)

Classification by function: Storage bus: CPU and memory System bus: Intermediate bus connecting the storage bus and IO bus IO bus: connecting external devices Classification by location: External bus: USB, Firewire (IEEE1394) Internal bus: PCI (connected to a network adapter), AGB (connected to a graphics card) (core) Intra-chip bus: Data bus: data transmission, bidirectional three-state address bus: address transmission, unidirectional three-state control bus: control signal and timing signal Power cable and ground cable: omitted 2. Bus performance and bus things

Bus performance parameters Bus frequency: Bus working rate F (in MHz) Bus width: data bus width W (in bit) Bus Transmission rate: BW (in MB/s) Amount of data transmitted by the bus. BW = W / 8 * F Bus transaction concept: sequence of operations from request bus to completion use (request – adjudication – address transfer – Data transfer – Bus release) Role: Master device (CPU, DMA) and slave device four stages: Request and mediation – Transfer – addressing – End Common bus operations: read, write, read modify write, read after write, block operation