• In the field of digital signal processing, a significant part of the work is post-processing, that is, using general-purpose computer systems to deal with such problems. There is another type of digital signal processing that must be completed within a specified time.
• Some digital signal processing is very demanding on time. Even high-speed general-purpose microprocessor chips cannot perform the necessary calculations in the required time. Therefore, it is necessary to design a special high-speed hardware logic circuit for such operation, and implement it on high-speed FPGA device or make it into high-speed special-purpose integrated circuit.
• Digital signal processing system consists of a high-speed dedicated digital logic system or a dedicated digital signal processor, usually including high-speed data channel interface and high-speed algorithm circuit.
• Modern asIC Design is accomplished by means of Electronic Design Automation (EDA) tools. Because the design of modern complex digital logic system is completed by means of EDA tools, both the simulation and synthesis of circuit system need to master the hardware description language.
• In order to accurately represent the information of a particular problem and to solve the relevant computational problems smoothly, it is necessary to adopt some special methods and build corresponding models. An algorithm is a sequence of steps to solve a particular problem; Data structures are models that solve specific problems.

C and HDL

• The advantages of HDL programming hardware are easy to understand, easy to maintain, debugging circuit speed, there are a lot of easy to master simulation, integration and layout wiring tools, but also can use C language with HDL to do logic design before wiring and wiring after simulation, verify whether the function is correct.
• During the development of the algorithm hardware circuit, the structure of the computing circuit and the technology of the chip have a great influence on the running speed, so before the circuit structure is completely determined, it must be simulated for many times, namely:

1. C language function simulation;
2. C language parallel structure simulation;
3. Behavior simulation of Verilog HDL;
4. Verilog HDL RTL level simulation;
5. Integrated backdoor structure simulation;
6. Simulation after layout and wiring;
7. Circuit simulation.

C with Verilog HDL design algorithm hardware circuit to consider three issues:

Why choose C language to work with Verilog HDL?

First, C is flexible and error-prone, and you can write your own system tasks through PLI (Programming language interface) and use it directly with hardware emulators. C language is the most widely used programming language in the world. Therefore, the design environment of C language is more complete than Verilog. C language has a reliable compilation environment, complete syntax, fewer defects, can be used in many English. By comparison, Verilog is only for hardware description and is not convenient to use elsewhere (for algorithm expression, for example). Both the integrity of C language and Verilog’s accuracy of hardware description should be used to design a hardware circuit system that meets performance requirements faster and better. With C’s complete error checking and compilation environment, designers can first design a functional correct design unit, which can be used as the standard for design comparison. Then, the C program is rewritten paragraph by paragraph into a parallel structure (similar to Verilog) describing the C program, still in THE C environment, using THE C language. If the running result is correct, replace the C language keyword with the corresponding Verilog keyword and enter the Verilog environment. Add the test input to C and Verilog at the same time, compare the output, find the problem, make correction, and test until the test passes.

What are the limitations of C language and Verilog HDL?

Verilog syntax that can be used for synthesis is limited, and no corresponding keyword can be found to replace the keyword in C. Verilog has few input and output functions available, and C has many variations. C function calls are different from Verilog module calls. C is executed line by line and belongs to a sequential structure. Verilog describes hardware that can be executed at the same time, which is a parallel architecture.

How to use C language to speed up hardware design and fault detection?

• C can be used in conjunction with Verilog to assist in hardware design.
• C is similar to Verilog in that, with some restrictions, C programs can easily be converted to Verilog behavior programs.

Verilog and VHDL:

VHDL — VHSIC Hardware Description Language, VHSIC — Very High Speed Integrated Circuit

Can formally and abstractly represent the behavior and structure of a circuit; Support the description of level and scope in logical design; The delicate structure of high-level language can be borrowed to simplify the behavior and structure of circuit; With circuit simulation and verification mechanism to ensure the accuracy of design; Support comprehensive conversion of circuit description from high level to low level; Hardware descriptions are independent of the implementation process (process parameters can be included through language-provided attributes); Easy document management; Easy to understand and design for reuse.

Comparison of Verilog HDL and VHDL modeling capabilities:

Verilog HDL is generally considered to be slightly worse than VHDL in system level abstraction and much better than VHDL in gate level switch circuit description. VHDL does not have the description ability of transistor switching level simulation design, but it is more suitable for very large system level logic circuit design. The underlying VHDL design environment is supported by a device library described by Verilog HDL.

• System level: a model of the system (the external performance of the module to be designed) that can be implemented with high-level structures provided by the language.
• Algorithm level: a model in which an algorithm can be implemented using a high-level structure provided by the language.
• Register Transfer level (RTL) : A model describing the flow of data between registers and how to process and control the flow of data.

The above three kinds of behavior description, only RTL level has a clear relationship with logic circuit. Gate level: A model describing the connections between logic gates and logic gates, having exact connections to logic circuits. Switch level: Model describing the triode and memory node in a device and the connection between them.

Behavior description/structure description

• Behavior description is described by the corresponding relationship between input and output, only the function description of the circuit, no structure description, and no specific hardware schematic diagram.

• Structural description is described by the connection of low-level elements or basic units, focusing on the function and structure of the circuit. It designs specific hardware to facilitate subsequent integration.

CPLD/FPGA

• Programmable Logic Device (PLD
• CPLD — Complex Programmable Logic Device
• FPGA — Field Programmable Gate Array
• PLD was first based on read-only memory (PROM), consisting of fixed and array and programmable or array, and then also based on electrically erasable read-only memory EEPROM.
• A CPLD contains at least three structures: programmable logic macro unit, programmable I/O unit, and programmable internal wiring. Is a kind of digital integrated circuit that users construct logic function according to their own needs.
• FPGA is based on look-up table LUT, its essence is to store all logical possibilities in RAM; The CPLD is based on the product of and – or.
• Different from gate array PLD, FPGA is composed of many independent programmable logic modules (CLB), which can be flexibly connected to each other. CLB is powerful and can not only realize logical functions, but also be configured into complex forms such as RAM. The configuration data is stored in the SRAM of the chip, and the logic function of the device can be modified on the spot, which is called field programmable. It provides rich programmable logic resources, easy to use storage/computing function modules and good performance, which not only solves the shortage of customized circuits, but also overcomes the shortcomings of the limited number of gates of the original programmable devices.
• FPGA internal structure trigger ratio and number is large, more suitable for sequential logic design; CPLD has the characteristics of abundant and or gate logic resources and not easy to lose when the program is powered off. It is suitable for designing and decoding combinational logic circuits.
• FPGA is more integrated than CPLD and has more complex wiring structure and logic implementation.
• CPLD is fast and has a large time predictability (continuous wiring structure) (CPLD structure provides a very good combination of logic implementation ability and the predictability of in-chip signal delay), FPGA piecewise wiring. CPLD has good confidentiality, FPGA has poor confidentiality. FPGA has greater flexibility in programming. CPLDS are programmed by modifying logic functions that have fixed internal circuits, and FPGas are programmed by changing the wiring of internal wires. CPLD has high power consumption and higher integration.

supplement

HDL Design and Validation Process (Easily Become a Master Designer)

System and function module definition (System and function module level),

In the design and implementation of large-scale systems, detailed system planning and description should be carried out first. At this time, HDL description focuses on the division and implementation of the overall system. System-level simulation focuses on the function and performance of the whole system. Functional module design divides the overall function of the system into specific functional modules that can be realized, and roughly determines the interface between modules, such as clock, read and write signals, data flow, control signals, etc. In some cases, timing constraints for each module or process need to be described based on system requirements. In addition, it is necessary to measure the advantages and disadvantages of various implementation methods of the whole system, and select the design scheme with excellent system performance index and efficient implementation. Function module-level simulation only inspects the function and basic timing of each module. Often with C language or high degree of abstraction HDL language description, such as SystemC, SystemVerilog.

Behavioral Description Motivation (Behavioral Level)

The biggest feature of behavior-level module descriptions is that all interfaces and boundaries between each module must be defined. At this point, the internal functions of the module have been clearly defined. All interfaces between modules and input and output signals at the top level have been clearly described at the behavior level. A common behavior level description is writing test incentives. Commands such as delay excitation and monitoring description are commonly used in the process of writing test excitation. Behavior level description is commonly used Verilog and VHDL.

Register Transfer Level (RTL)

Register transfer level refers to the HDL level that describes the circuit through register-to-register logic functions without paying attention to the details of registers and combinatorial logic (such as how many logic gates are used, the topology of connections between logic gates, etc.). RTL level is a higher level of abstraction than gate level. Generally, it is simpler and more efficient to describe hardware circuits with RTL level language than with gate level language. The main feature of RTL description is that it can be synthesized directly into gate level netlists using synthesis tools. RTL design directly determines the function and efficiency of the design. A good RTL design can achieve a balanced optimization of design speed and area on the premise of satisfying the logic function. RTL description is commonly used Verilog and VHDL.

Conduct behavior simulation for RTL level description

Generally speaking, functional simulation of RTL level design is required to verify whether the RTL level description is consistent with the design intention. In order to improve efficiency, the test motivation of general function simulation is described using behavior-level HDL language.

Logical synthesis (using RTL level EDA tools)

RTL level synthesis refers to the translation of RTL level HDL language into gate-level connection (netlist) composed of basic logic units such as and or not gates, and optimization of the generated logical connection according to the design objectives and requirements (constraints), and output gate-level netlist files. With the continuous intellectualization of comprehensive tools, it is more and more convenient to use RTL language to describe hardware circuits, especially in the field of PLD design, the most important design level is RTL level.

Gate level

At present, most OF FPGA design relies on professional synthesis tools to complete the conversion from RTL code to gate code, so designers directly describe gate level model with HDL language is less and less, and efficient synthesis tools completely free designers from tedious description of gate level. The characteristic of gate level description is that the whole design is realized by logic gate, and all the information such as pins, functions and clock cycles are described through the combination of logic gates.

Integrated backdoor level simulation

After the completion of synthesis, if it is necessary to check whether the synthesis results are consistent with the original design, it is necessary to do post-synthesis simulation. During the simulation, the standard delay file generated by the synthesis is backward marked into the synthesis simulation model, so that the influence of gate delay can be estimated. Although the integrated simulation is more accurate than the functional simulation, but can only estimate the gate delay, can not estimate the impact of the gate delay, simulation results and wiring after the actual situation there is a certain gap. The main purpose of this simulation is to check whether the synthesis result of the synthesizer is consistent with the design input.

Layout planning and layout and wiring

The integrated gate results are eventually mapped to the target library (ASIC design) or target device (PLD design).

Time sequence simulation and verification after layout and wiring

When the delay information of the final layout planning or layout and wiring is invert marked in the design net list, the simulation designed is called timing simulation or layout planning and layout and wiring post-simulation, or post-simulation for short. After layout planning and layout and wiring, the generated simulation delay file contains the most complete delay information, including not only gate delay but also actual wiring delay, so the timing simulation is the most accurate and can better reflect the actual working situation of the chip. Generally speaking, it is recommended to conduct timing sequence simulation first, through which the design timing sequence can be checked to ensure the reliability and stability of the design. Timing Violation the primary purpose of timing simulation is to detect Tinming Violation situations in which timing constraints or inherent device scheduling rules (setup time, holdtime, etc.) are not met.

The two most important roles of HDL language are: using HDL language to describe circuits efficiently at the RTL level; Describe test incentives at the behavior level.