What is the I2C

The I2C bus was designed by Philips in the early 1980s to allow easy communication between components located on the same circuit board. It greatly simplified the design of circuits, and I2C communication was used in many parts of early television sets. Philips Semiconductor moved to NXP in 2006. I2C name translates to “Inter IC”. Sometimes, this bus is called the IIC or I²C bus. I2C summarizes the basic characteristics:

  • The circuit is simple, only need two lines, clock line SCL and data line SDA
  • The I2C is a bus structure, and the primary device is addressed by the secondary device address
  • Devices on the I2C bus can be one master with multiple slaves or multiple masters with multiple slaves. In the multi-master and multi-slave mode, arbitration and conflict detection mechanisms are required.
  • The I2C master provides a clock and the SDA can transmit data in both directions
  • The transmission rate of I2C standard can reach 100Kbit/s, 400Kbit/s in fast mode, and 3.4Mbit/s in high speed mode. The most commonly used transmission rate is less than or equal to 100Kbit/s.

I2C hardware circuit

I2C master-slave hardware connection circuit is as follows:I2C hardware circuit features:

  • The device connected to the I2C bus must be connected in an open-drain or open-collector manner in order to achieve line and.
  • The SCL and SDA must be attached to a pull resistor between 4.7K and 10K.
  • The number of devices connected to the bus is limited by a 400pF capacitor.

Here need to pay attention to the three points: open leakage or open collector, pull up resistance, wire and, the following are discussed. Need to realize the explanation is that I am not electronic professional graduation, if there is something wrong, welcome to criticize.

Open drain/collector

The SDA and SCL of the chip must be connected to the I2C bus in an open-drain or open-collector manner.

First of all, what is the drain/open collector, the following transistor collector open as an example to explain, MOS tube drain open principle is similar.The above figure is the open collector connection of the triode. The characteristics of this connection are as follows:

  • The input terminal is “1”, that is, high level, the triode is on, the TRIode C pole and E pole are on, and the output is “0”.
  • The input end is “0”, that is, low level, the audion cut-off, the audion output “1”.
  • The input and output are inverting.
  • If the output is not connected with a pull resistor, if the input is “0”, the output is “high configuration”.
  • The input terminal can output only 0 but cannot output 1. If you want to output 1, connect an external pull-up resistor.
  • The functions of “line and” can be implemented, as described in the next section.
  • Electrical compatibility is good, pull-up resistance connected to different voltages can be connected to different systems, connected to 3.3V to 3.3V system, connected to 5V to 5V system.

The above is the collector open hardware circuit of the triode. However, there is a problem, that is, the input and output are inverting. It needs an additional circuit to “inverting” it again to make the input and output consistent.

In the circuit above, an inverting triode is added, namely, Triode 2. Here is a look at its input and output characteristics:

  • The input end is “1”, that is, high level. The transistor 1 is on and the transistor 2 is off. The output end is “1” due to the “open collector” and the role of the pull-up resistor.
  • The input terminal is “0”, that is, the low level, the transistor 1 cut-off, the transistor 2 conduction, then the output terminal output is “0”.

You can see that the phase of the input and the output are the same. Ok, above is the principle of the open collector circuit of the triode, then, why is it necessary to connect the device to the I2C bus in an open leak or open collector way? The fundamental reason is that this kind of circuit can realize the function of “wire and”.

Line with

Because I2C is a bus communication protocol, there are multiple devices mounted on the two signal cables of I2C. The principle of device communication is to change the level of SDA regularly according to the clock on SCL to meet the requirements of data communication. Since multiple devices are connected to the bus, it is inevitable that multiple devices will try to change the level on the signal line at the same time, so conflicts will inevitably occur. Therefore, if communication is to be normal, conflicts must be avoided. A simple conflict prevention mechanism is that the device needs to conduct conflict detection before sending data. The detection is based on checking the level status of SDA: As long as the SDA is detected as low, it indicates that the bus is in the occupied state. In order to avoid conflicts, the current device must wait for a period of time to detect the SDA level again. If the bus becomes “idle” (that is, the SDA is high), then the device can communicate.

Here is a key point: how to ensure that multiple devices connected to the I2C bus, as long as one device existsTake upNo other device can make the bus becomefree? The open collector structure described above can meet this requirement.As shown in the figure above, the SDA output values for each device are not exactly the same, but as long as one of them is “0”, the result is “0”, that isLine with, which can ensure that the signal on the SDA line is either stable as “0” (at least one device output is 0) or stable as “1” (all devices output is 1). Using the “line and”, the device on the I2C bus can easily detect the working state of the bus, so that conflict detection and normal communication timing can be realized.

I2C sequence

The above mainly introduces the basic hardware principle of I2C bus. However, to complete the final communication between devices, the interaction of different signals must be completed in strict accordance with certain timing, which is the hardware protocol of I2C communication.

Edge control signal

When an I2C device communicates, the primary device initiates the communication. If the master device is writing data to the slave device, the master device puts the data in the SDA. After the data is stable, the master device sends a rising edge to the SCL to notify the slave device to read the data. During the high level of SCL, the data in the SDA should be stable. If the master device is reading data from the slave device, the master device sends a falling edge to the SCL to notify the slave device to put the data on the SDA. The master device reads the data on the SDA during the high level of the SCL. The data on the SDA must be stable during the reading period.

To summarize:

  • Write: The master device places the data on the SDA. When the data is stable, the master device sends an edge signal (rising edge) to notify the slave device to read the data on the SDA.
  • Read: The master sends an edge signal (falling edge) to tell the slave to send data. After the edge signal is detected, the slave changes the data, and the master reads the data while the clock is high.

Data validity requirement

  • During I2C data transmission, the data on the SDA must be stable when the SCL is high.
  • The data on the SDA is allowed to change only when the SCL is low.

Start/stop signal

I2C start and stop signals are as follows:

  • Both the start and stop signals are initiated by the master device.
  • After the start signal, the bus is in the occupied state, and after the end signal, the bus returns to the idle state.

The data transfer

The general rules for I2C data transmission are as follows:

  • Each byte sent to the SDA line must be 8 bits, and there is no limit to the number of bytes that can be sent per transmission.
  • The highest bit of data (MSB) is transmitted first. Each byte must be followed by a response bit, so there are 9 bits in a frame.
  • If the slave has to perform some other function (such as an internal interrupt service routine) before receiving or sending the next complete data byte, the clock line SCL can be kept low, forcing the host into a wait state, and data transmission can continue when the slave is ready to receive the next data byte and the clock line SCL is released.

After receiving the data, if the receiver needs to continue to receive the data, it needs to send the data to the senderThe replySignal; If the data receiver does not receive any more data, send the dataNot replyThe signal.

Read/write timing

Equipment addressing

When I2C begins communication, the master device initiates bus addressing by sending a one-byte addressing address after initiating the initial signal.

  • R/W bits: indicates the data transmission direction. 0 indicates that the host writes data to the slave, and 1 indicates that the host reads data from the slave.
  • Device address is divided into programmable and non-programmable, some device address is fixed, and some devices can be set through the pin of the chip device address, address programmable devices, convenient in an I2C bus, connected to multiple identical devices, and then by the address to distinguish.

I2C write sequence

The following figure shows a complete sequence diagram of the host writing a byte to the slave. Note the following:

  • After the start signal, the host needs to send the addressing byte first, where, the 0 bit, 0 indicates that the host will write data to the slave machine.
  • After receiving each data, the slave machine needs to send an ACK signal to indicate that the data has been successfully received.
  • After sending data, the host sends a stop signal.

The I2C read sequence

The following figure completely shows the time sequence diagram of the data being read by the host from the slave. It should be noted that:

  • After the start signal, the host needs to send the addressing byte first, where, the first bit, 1, means that the host read the data from the slave machine.
  • After receiving each piece of data, the host sends an ACK signal to indicate that the data is successfully received.
  • After receiving the last byte of data, the host sends “NACK” to indicate the completion of receiving. After that, the slave machine gives up the control of SDA, the host sends a stop signal, and the data receiving process ends.