1. ARM32 profile

The ARM processor has 32 registers, of which 31 are general purpose registers and 6 are status registers.

The ARM processor supports seven modes: user mode, Fast Interrupt mode, and 3. External Interrupt mode, 4. Management mode, 5. Data access termination mode, 6. The specified abort mode is not defined.

STMFD and LDMFD are generally used for on-site PROTECTION of CPU before large-scale operation such as program moving and on-site recovery after operation, which belong to non-single continuous stack pressing and stack exiting.

Arch specifies the architecture of the ARM processor.

Instructions beginning with a “.” in a program are assembler instructions. Assembler instructions are assembler dependent and do not belong to the ARM instruction set.

The assembler instructions are as follows:.file: specifies the source file name,.aligan: specifies the alignment of the code, followed by a value raised to the power of two. .ascii: a declaration string. Global: Declares a global symbol. Type: Specifies the type of the symbol. Word: used to store the address value. Size: Sets the size of the specified symbol.

2.ARM processor addressing mode

Immediately addressing: mov R0, #1234, R0= 1234, immediately prefixed by “#”, indicating that hexadecimal values start with “0x”, such as #0x20

Register addressing: e.g. Mov R0, R1 after execution R0= R1

Register shift addressing: for example: mov R0, R1 LSL #2: shift R1 register to the left by 2, that is, “R1 << 2” after assigning to register R0, R0=R1*4 after execution

Shift operation instruction: LSL: logic shift left, after shift register empty low complement 0, LSR: logic shift right, after shift register empty high complement 0. If the operands are positive, then the upper part of the shift is filled with 0. If the operands are not positive, then the upper part of the shift is filled with 1. RRX: the extended loop is shifted right, the operands are shifted right, and the high position vacated by the shift is filled with the value marked by C.

Register indirection: for example, LDR R0, [R1] : take the value in register R1 as the address, and assign the value from the address to register R0. Base addressing (mostly used for table lookup and array access) : for example, LDR R0, [R1, #-4]: subtract 4 from the value in register R1 and assign the value of this address to register R0.

Multi-register addressing: LDMIA R0, {R1, R2, R3, R4} : LDM is a data loading instruction, the suffix IA of the instruction means that the R0 register value increases by 1 word after each loading operation, and the ARM instruction set word represents a value of 32. This instruction execution R1 = (R0), R2 = [R0 + # 4], = [R0 + # 8] R3 and R4 = [R0 + # 12]

Stack addressing: the stack addressing instructions are: LDMFA/STMFA,LDMEA/STMEA, LDMFD/STMFD,LDMED/STMED. Where LDM and STM are prefixes of instructions, representing multi-register addressing. Such as: STMFD SP! ,{r1-r7, LR}: push R1~R7, LR into the stack, mostly used to save the scene of subroutine. LDMFD SP! , {r1-R7, LR} put the data out of the stack and put it in the R1-R7, LR register. Mostly used to recover the subroutine site.

Copy copy addressing: blocks of addressing instructions are: LDMIA/STMIA, LDMDA/STMDA, LDMIB/STMIB, LDMDB/STMDB such as: LDMIA R0! , {R1-R3} reads 3 words from the storage location pointed to by register R0 into registers R1-R3. STMIA R0! , {R1-R3} stores the contents of registers R1-R3 to the storage location pointed to by register R0. The Thumb instruction set is a subset of the ARM instructions.

3. Data register

Data registers: R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12 Stack pointer: R13 points to the top of the current stack, which is equivalent to the X86 ESP, and should be represented by sp in the assembly instruction. Link register: R14 points to the return address of the function. Let’s call it LR. Program counter: R15 This is similar to the X86 EIP, temperament is equal to the address of the instruction being pointed to +8, in PC. Processing status register: THE CSPR is used to monitor and control internal operations.

4. Conditional flag bit

N, Z, C, and V are all conditional code flag bits. N is a positive or negative flag, N=1 means the result of the operation is negative, N=0 means the result of the operation is positive or 0, Z is a zero flag, Z=1 means the result of the operation is 0, Z=0 means the result of the operation is non-0, C is a carry flag, if the addition operation produces a carry, C=1, otherwise C=0. C: borrow flag, if subtraction produces a borrow flag, it is 0, otherwise it is 1. V: overflow flag, V=1 means overflow, V= 0 means no overflow.