1.ARM32 common instruction parsing

ADC carries addition instruction, ADD addition instruction, AND logic AND instruction, B branch instruction, BIC bit clear zero instruction, BL with return branch instruction, BLX with return AND state but change branch instruction, BX with state but change branch instruction. CDP coprocessor data operation instruction, CMN comparison inverse instruction, CMP comparison instruction, EOR xOR instruction, LDC memory to coprocessor data transfer instruction LDM load multiple register instruction, LDR memory to register data load instruction, MCR data transfer instruction from ARM register to coprocessor register, MOV data transfer instruction, MRC data transfer instruction from coprocessor register to ARM register MUL 32 bit multiplication instruction MLA 32 bit multiplication instruction. MRS transfers the contents of CPSR or SPSR to the general register instruction, MSR transfers the general register to CPSR or SPSR instruction, MVN data fetch and reverse transfer instruction, ORR logic or instruction, RSB reverse subtraction instruction, RSC reverse subtraction instruction with dislocation, SBC with dislocation subtraction instruction, STC coprocessor register write memory instruction, STM batch memory word write instruction, STR register to memory data storage instruction, SUB subtraction instruction, SWI software interrupt instruction.

A single instruction can complete the transfer of multiple register values (up to 16 general purpose registers), use “-” for continuous registers, otherwise use “,”

2. Use of key assembly instructions

STMFD and LDMFD have the same effect as x86 assembly push and pop.

LDR R4, START reads the word data stored at the START address into R4 STR R5, DATA1 stores R5 as DATA1. LDR R0, [R1] writes word data from memory address R1 to memory R0 LDR R0, [R1,R2] reads word data from memory address R1+R2 into memory R0 STR, R0, [R1, #8]! R0 STR, R0, [R1,R2]; R0 STR, R0, [R1,R2]; R0 word data is stored in memory R1+R2 storage unit, and the new address R2+R2 is written to R2

Push {r0, r4-R7} push the contents of registers R0, R4-R7 onto the stack pop{r0,r4-r7}} Pop the contents of registers R0, R4-R7 off the stack

LDM instructions are used for stack exit and STM instructions are used for stack entry.

3. Introduction to the jump instruction

B Unconditional jump BL Unconditional jump with band connection BX Unconditional jump with state change BLX Unconditional jump with band connection and state change

4. Storage instructions detailed explanation

LDR: Load LDR R8, [R9, #04]: R8 is the register where the data is to be loaded, and the Load value is the storage unit pointed to by R9+0x4

–store STR R8, [R9,#04]: Stores the data in register R8 to the storage location pointed to by R9+0x4

LDM: load the data of memory into the register list → LDM R0, {R1-R3} Load the data of the storage unit pointed by R0 into registers R1,R2 and R3 in turn

STM: stores a list of registers into a specified memory PUSH: pushes register values onto the stack POP: pushes stack values onto the register SWP: exchanges data between registers and memory SWP R1, R1 [R0] exchanges the contents of register R1 with the storage location pointed to by R0

5. Register details

The ARM32 assembler has predefined ARM registers, and all register and coprocessor names are case sensitive, RO-R15 and R0-R15.

A1-a4 (parameter, result or temporary register, same as R0-R3)

V1-v8 (variable register, same as R4-R11)

Sb and SB(static base address registers, same as R9)

Sl and SL(stack limit register, same as R10)

Fp and FP(frame pointer, same as R11)

IP and IP(temporary registers between procedure calls, unified with R12)

Sp and SP(stack pointer, unified with R13)

Lr and LR(connected register, unified with R14)

PC and PC(program counter, unified with R15)

CPSR and CPSR(Program Status Register)

SPSR and SPSR(Program Status Register)

F0-f7 and F0-F7(FPA register)

S0-s31 and S0-S31(VFP single precision register)

D0-d15 and D0-D15(VFP double precision register)

P0-p15 (coprocessor 0-15)

C0-c15 (Coprocessor registers 0-15)

6. Assembler uses the required concerns in functions:

1. When the function parameters are less than 4, the subroutines pass the parameters through registers R0-R3; When the number of parameters is more than 4, the redundant parameters are passed through the data stack. The push order is opposite to the parameter order. The values of R0 to R3 do not need to be restored before the subroutine returns.

2. In the subroutine, use R4~R11 to save local variables. If the use needs to be stored on the stack, these registers need to be restored before the subroutine returns; R12 is a temporary register and does not need to be saved to use. 3.R13 is used as data frame pointer, denoted as SP; R14 is used as the link register, known as LR, and is used to store the address when the subroutine returns; R15 is the program counter, I’ll call it PC. 4.ATPCS specifies that the stack is full descending the stack FD; 5. Subroutine return 32 bit integer, use R0 return; When returning a 64-bit integer, use R0 to return the low value and R1 to return the high value.