Hello everyone, I am a ruffian balance, is a serious technical ruffian. Serial NOR Flash does not download/start properly in I.mx.

It has been more than two years since the release of I.MXRT series MCU, and more and more customer products based on I.MXRT are coming into full bloom. Ruanziheng, as a system application engineer for the I.MXRT product line, was free to do reference design in the early days, but now spends most of his time on customer support.

Since i.MX series do not have built-in Flash (except RT1064, RT1024 and other SIP models), it is a top priority for customers to start with a serial NOR Flash. There are many serial NOR Flash manufacturers, and customers have a large choice. So we have to deal with customers with the vast number of Flash models, Ruffian balance also often joke that he has become a Flash test engineer.

Ruffian balance in support of customers to solve the serial NOR Flash download start problem process encountered several common factors, these factors may affect Flash in I. MX can not be used normally, the last chapter Ruffian balance said “SFDP factors”, today ruffian balance focus on chat with you QE bit this factor.

What is QE bit?

QSPI NOR Flash (ISSI IS25WP064AJBLE) is the default placement on the I.MXRT EVK to explain this concept.

1.1 QE to define

The following is the pin diagram of the IS25WP064AJBLE, the most classic QSPI NOR Flash package (SOIC-8), with 8 pins, minus the necessary power and ground, and 6 signal cables. The 6 signal cables are pin1/2/5/6 enclosed in blue boxes, which are common SPI interfaces in embedded communication. In addition, there are two signal lines pin3/7 enclosed in green boxes, which are functional reuse. To explain QE, it is related to its two functional positioning.

QE to put it more simply, pin3/7 is used for IO2/3 when data transfer function, i.e. QE enabled; Pin3/7 used for WP#, HOLD# control functions is QE disabled.

1.2 QE meaning

QE does not enable pin3/7 to be used for WP# and HOLD# functions. This is well understood as an external pin level setting to protect Flash data (mainly from being overwritten). So what does QE enable mean? This starts with the QSPI NOR Flash mode.

A standard NOR Flash operation sequence consists of CMD + ADDR + dummy + DATA, which determines the Flash operation mode. Broadly speaking, Flash can be divided into two modes, namely SPI mode and QPI mode:

  • SPI mode: DATA line IO0 is the eldest, CMD can only be sent by IO0, and other data transmission can be sent together with IO[3:1] (there are many ways to do this, which will be introduced later)
  • QPI mode: the four data lines IO[3:0] are in equal status, and all data transmission is carried out by the four brothers together, which is the highest in terms of I/O efficiency.

By default, the Flash chip is powered on in SPI mode. You need to send a special command (qpien-0x35) in SPI mode to enter QPI mode. After entering QPI mode, the QE control function does not take effect (no matter what QE setting is, it is equivalent to the QE enabled state). The reason is that IO[3:0] must be loaded together in QPI mode. Since I.mx BootROM does not support QPI mode by default (you can do that if you want, but it’s a hassle), we will only discuss SPI mode.

Flash operations are mainly read, write, and erase. We will discuss the SPI mode in terms of the most common read. Go on to the IS25WP064AJBLE manual and find its command set. You can see that there are a lot of read related commands, a total of 9. Not counting DTR (bilateral edge sampling), there are 6 kinds of light SDR (single edge sampling), Rascal heng said before, SPI mode IO[3:0] specific how to transmit data in many ways is reflected here.

Normal Read Mode (NORD-0x03) and Fast Read Quad I/O (FRqIO-0xEB) are the most efficient. As can be seen from the following figure, in NORD mode (left), only IO[1:0] is used. IO0 is responsible for sending commands and addresses, while IO1 is responsible for receiving data, and SCK is up to 50MHz. In FRQIO mode (right in the figure below), except for IO0 sending commands, other addresses and data are completed by IO[3:0], and SCK can reach 133MHz, which is as efficient as QPI mode.

To get the most out of Flash for code execution (XIP), we definitely want Flash to work in FRQIO mode, which obviously depends on the QE Settings.

2. QE bit position difference

How to set QE function in Flash? In fact, in addition to Memory blocks, Flash usually has some registers to record user configuration or save state.

2.1 Several different QE bit designs

The following is the Status Register of IS25WP064AJBLE, which has only one SR, where SR1[6] is the QE bit used to set the QE function, and it should be noted that the QE bit is non-volatile, which means that even if the Flash is powered down, This QE setting is still in place.

In IS25WP064AJBLE there is a CMD for reading and writing SR, where WRSR is the common 0x01:

Is it true that all Flash vendors design QE bits in this way? Sadly, no! The SR2[1] is the QE bit: W25Q64JVSIM: SR2[1]

W25Q64JVSIM has three sets of CMD, where write SR2 command word 0x31 is used to set QE:

It seems that in QE bit design this piece, the Flash manufacturers are not necessarily the same, according to what ruffian balance knows, there are at least four different QE bit design on the market, ruffian balance is not a list. What’s more, the QE design of different Flash series from the same manufacturer may be different, such as The Flash of Mega Easy Innovation.

2.2 SfDP-JESD216A specification

What if it becomes a little difficult to turn QE on with one set of software drivers for different QE bit designs? Then JEDEC stood up. Ruffian Heng mentioned in the first section of SFDP Factors that FIVE versions of JESD216 standard have been developed since 2011. There is no definition of QE bit position in the original version JESD216 (Basic Flash Parameter Table in SFDP only contains 9 DWords). Since JESD216A, QE bit position information has also been recorded in SFDP Table (Basic Flash Parameter Table expanded to 16 DWords). QE bit information is recorded in Table 15 below:

Therefore, if the Flash does not support SFDP or is only SFDP of JESD216, you need to manually check its data manual to find the QE bit information. And JESD216A and above version of Flash, we can read SFDP table directly to know QE bit information.

3. Default QE bit status

Now that we have a comprehensive understanding of the QE bit, there is one last question: what is the initial state of the QE bit when the Flash is shipped from each manufacturer? According to Ruffian Balance understand, each manufacturer almost at the same time have QE default is on or off Flash model, this will be reflected in the Part Number, such as the following W25Q series naming rules, the last one represents the default QE status:

Other Flash vendors have different naming rules for QE status, so you need to check your manual for details.

How to handle Flash with different QE bits in I. mx

The first step is to check whether Flash has SFDP and specify its SFDP version.

4.1 Specifying the SFDP version

Take the default Flash IS25WP064AJBLE on I.maxRT EVK as an example. According to the data manual, it supports SFDP, but the specific JESD216 version cannot be found, so we need to read SFDP directly from Flash. Minor Revision found in the first Parameter Header is 0x06, JESD216B.

enum
{
    kSfdp_Version_Major_1_0 = 1,
    kSfdp_Version_Minor_0  = 0.// JESD216
    kSfdp_Version_Minor_A  = 5.// JESD216A
    kSfdp_Version_Minor_B  = 6.// JESD216B
    kSfdp_Version_Minor_CD = 7.// JESD216C, JESD216D, JESD216D.01
};
Copy the code

4.2 Setting QE information to download

Because the SFDP version of IS25WP064AJBLE is relatively high, the QE information of IS25WP064AJBLE can not be checked in the manual. If the Flash does not support SFDP or SFDP is the first version, you need to check the data manual to record the QE bit position and initial status.

We know that both Jlink and the major IDE download algorithms and the MCUBootUtility tools are designed with the same download algorithm for I. Mx, as in Section 2.2 of ROM API for IAP. For the classic four-wire QSPI NOR, we simply change the option value.

For IS25WP064AJBLE under I.maxrt1060, we directly set option = 0xC0000008. The speed is 133MHz. QE is NotConfig by default (note option[11:8] indicates QuadMode). Why QE is NotConfig? That’s because the SFDP version of Flash is high, and the download algorithm can find QE information in SFDP and try to enable it.

enum
{
    kSerialNorQuadMode_NotConfig = 0,
    kSerialNorQuadMode_StatusReg1_Bit6 = 1,
    kSerialNorQuadMode_StatusReg2_Bit1 = 2,
    kSerialNorQuadMode_StatusReg2_Bit7 = 3,
    kSerialNorQuadMode_StatusReg2_Bit1_0x31 = 4};Copy the code

If Flash is not SFDP or JESD216 and QE is turned off by default, option[11:8] must be set correctly, otherwise an error will be reported during download verification. For example, W25Q64JVSIM, SFDP version is not sure, just to be safe, we can directly set option = 0xC0000408.

The option QE setting above corresponds to the MCUBootUtility download utility:

4.3 Match FDCB to boot

If you can successfully open QE in Flash when downloading, i.mx will start with nothing special, just FDCB provided in the SDK. In order to achieve maximum XIP performance, the LUT in FDCB is equipped with four-line I/O mode Fast Read, and QE is already on, so the CPU will not have any problem reading instructions in Flash.

Serial NOR Flash does not download/start properly in i.mx

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