“This is the second day of my participation in the First Challenge 2022.

preface

When building an application on Linux or Unix, the make XXX command is often used to install dependencies for the application.

What is make?

Make is a Utility software program that automates the construction of software by reading “makefiles”. It is a tool for converting file form. The target of conversion is called “target”. At the same time, it checks for file dependencies and, if needed, calls some external software to do the job.

As the name implies, make is, of course, for creation. Its function is to build applications based on the description of a Makefile that defines a set of tasks to be performed. As with the NPM package manager in front-end development, we need a package.json to describe the dependencies we need.

After the make command is executed, a file named Makefile or Makefile is found in the current directory.

Make has the following capabilities:

• Make enables the end user to build and install a package without knowing the details of the build, because those details are recorded in the makefile provided by the application.

• Make automatically calculates the files that need to be updated based on the changed source files. It also automatically determines the correct order in which to update files, in case one non-source file depends on another.

  So, if you change some source files and then run Make, it doesn’t need to recompile all of your programs. It only updates non-source files that are directly or indirectly dependent on the source file you changed.

• Make does not qualify languages. For each nonsource file in the program, the makefile specifies the shell command to evaluate it. These shell commands can run the compiler to generate object files and run the linker to generate executable files.

• Make is not limited to building a package. You can also use Make to install or uninstall packages and generate label tables for them. You can also write commands that need to be executed at build time, like the scripts field in p ackage.json.

The makefile grammar

To put it simply, many scripts are integrated in the Makefile. When we use make XXX command, we will make a conditional judgment on the XXX we pass in and see which one is matched and execute which script. Most of the syntax in makefiles is the same as shell or bash.

The basic format

# Indicate comments with a "#".Target: DependenciesThe # command is preceded by "TAB" instead of a space. Misuse of Spaces is a beginner's mistake!Command 1 Command 2 Command 3... Order nYou can use "\" to indicate a continuation. Note that there can be no Spaces after "\"!
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For example, we create a new makefile and write the following code to it:

.DEFAULT_GOAL := mkdir

hello:
        @echo "Hello I'm oil"

mkdir:
        @echo "create a new dir"
        mkdir test

rmdir:
        @echo "delete a dir"
        rm -rf test
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If we look at the code above, when we do make, we do it from the top down in the order we want to do it in our code, but instead of hello, we do mkdir, DEFAULT_GOAL := mkdir Because we wrote.default_goal := mkdir in the file header, if the Make command runs without specifying a target, the first target in the Makefile will be executed by default.

Target is required and cannot be omitted, while dependencies and the command to execute are optional, but at least one of the latter must exist.

A target makes a rule. Specifies the object to be built by the Make command. In addition to the file name, target can also be the name of an operation, also known as a pseudo target. PHONY: target can be defined using.PHONY: target.

.PHONY: help
help:
	$(call func_echo_success_status, "Makefile rules:")
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More built-in targets can be found in this document :www.gnu.org/software/ma…

Dependencies determine whether the target file is rebuilt. They are usually a group of file names separated by Spaces. If one of the preceding files does not exist or if the last-modification timestamp of the preceding file is newer than the target timestamp, the target file needs to be rebuilt.

a.txt:b.txt c.txt
       @echo "Hello I'm oil"

b.txt:c.txt
       touch b.txt

c.txt:
      touch c.txt  
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In the above code, if none of the three files exist, the first execution of make A.tuck will create c.tuck and b.tuck based on the dependencies, and the second execution will satisfy the dependency file generation required for A.tuck.

Define variables

Variables can be defined directly in makefiles using the = sign and used with $(variable name).

A = hello
B = world
hello:
        @echo $(A) $(B)
mkdir:
        @echo "create a new dir"
        mkdir test

rmdir:
        @echo "delete a dir"
        rm -rf test
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Close the echo

When executing a make command, if nothing else is done, the console prints each command by default to let the developer know which command is currently executing, which is the echo mechanism. If you want the console not to print, you can turn off the echo by prefacing the command with an @ sign.

test:
    @# Do not print content
    # Print content
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More makefile syntax you can view the document: gist.github.com/isaacs/62a2…

conclusion

It is the first time to write linux-related content. In order to learn the technology of the server side, there are still a lot of knowledge points waiting to learn. These days, I will start to explode