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Here we will introduce the relevant content of the register. As we know, the register is the internal structure of the CPU, which is mainly used for information storage. In addition, the CPU has an algorithm, which is responsible for processing data; The controller controls other components; The external bus connects the CPU and various components for data transmission. The internal bus is responsible for the data processing of various components within the CPU.

So for assembly language as we know it, our main concern is registers.

Why do registers appear? Because we know that programs are loaded in memory and run by the CPU, whose main job is to process data. So the process will inevitably involve the read and write data from memory, because it involves sending data through the control bus request and into the storage unit, through the same channel to get the data, this process is very cumbersome and will involve a lot of memory footprint, and there are some commonly used pages, is not necessary, so the register, It’s stored inside the CPU.

Recognition register

Processing Register (CPU Register) Processing Register (CPU Register) Processing Register (CPU Register)

Before we get to the registers, let’s first look at the internal structure of the CPU.

A CPU can be logically divided into three modules, namely, the control unit, the computing unit, and the storage unit. These three parts are connected by an internal CPU bus.

In almost all von Neumann cpus, the work can be divided into five stages: fetch instruction, decode instruction, execute instruction, access number, and write back result.

  • Instruction fetchA phase is the process of reading an instruction from memory into a register in the CPU that stores the address of the next instruction
  • Instruction decodeIn the stage of instruction decoding, the instruction decoder splits and interprets the retrieved instruction according to the predetermined instruction format, and identifies different instruction categories and various methods for obtaining operands.
  • An instruction toStage, after the completion of decoding, it is necessary to execute this instruction, the task of this stage is to complete the various operations specified by the instruction, specific realization of the function of the instruction.
  • Access to accessStage: according to the requirement of instruction, it may need to extract data from memory. The task of this stage is to obtain the address of the operand in main memory according to the instruction address code, and read the operand from main memory for operation.
  • Results to write backAs the last stage, the result Write Back (WB) stage writes the result data of the execution instruction stage Back to the internal register of CPU, so that it can be accessed quickly by subsequent instructions.

A register in a computer architecture

Register is a very fast computer memory, the following is the comparison of modern computers with storage functions of the components, it can be seen that the register is the fastest, but also the most expensive.

Let’s take the example of the Intel 8086 processor, the predecessor of the x86 architecture. The 8086 was followed by the 8088.

In the 8086 CPU, the address bus is up to 20, so the maximum addressing capacity is 2^20 or 1MB of addressing capacity. The same is true for the 8088.

In the 8086 architecture, all the internal registers, internal and external buses are 16 bits wide and can store two bytes because it is a full 16-bit microprocessor. The 8086 processor has 14 registers, each of which has a unique name, i.e

AX, BX, CX, DX, SP, BP, SI, DI, IP, FLAG, CS, DS, SS, ES

These 14 registers may be divided into three types according to their functions

  • Universal register
  • Control register
  • Segment register

Let’s look at each of these registers

Universal register

There are four general purpose registers: AX, BX, CX and DX. Similarly, these four registers are 16 bits and can hold two bytes. AX, BX, CX and DX registers are commonly used to store data and are also known as data registers. Their structure is as follows

8086 CPU’s previous generation register is 8080, it is a class of 8-bit CPU, in order to ensure compatibility, 8086 in the 8080 made a small change, 8086 general purpose registers AX, BX, CX, DX can be used independently with two 8-bit registers.

In detail, AX, BX, CX, DX can be further divided

  • AX(Accumulator Register): Cumulative register, which is mainly used for input/output and large-scale instruction operations.
  • BX(Base Register): Base address register, used to store the underlying access address
  • CX(Count Register): count register, CX register will loop count during iterative operation
  • DX(data Register): Data register, which is also used for input/output operations. It is also used with the AX register and DX for multiplication and division operations involving large values.

These four registers can be divided into upper and lower parts and used as eight 8-bit data registers

  • AX registers can be divided into two independent 8-bit AH and AL registers;
  • The BX register can be divided into two independent 8-bit BH and BL registers;
  • The CX register can be divided into two independent 8-bit CH and CL registers.
  • The DX register can be divided into two independent 8-bit DH and DL registers;

Except AX, BX, CX, DX registers above, all other registers can not be divided into two independent 8-bit registers

As shown in the figure below.

That’s the sum of

The low (0-7) bits of AX form the AL register, and the high (8-15) bits form the AH register. The AH and AL registers are available 8-bit registers, as well as others.

With registers in mind, let’s take a look at how data can be stored with an example.

For example, data 19, stored in 16-bit memory, is represented as follows

Register storage is to store the low first, if the low can not meet the high store, if the low can meet, the high complete with 0, in the case of other low can meet, the other bits also complete with 0.

The 8086 CPU can store two types of data at once

  • Bytes (byte): A byte consists of 8 bits, which is a constant storage mode
  • Word (word): word is fixed size data processed by instruction set or processor hardware as a unit. For Intel, a word is two bytes long. Word is a very important feature of computer. That is to say, according to the machine of different instruction set, can process not the word length at a time, have word, double word (32 bits), four word (64 bits) and so on.

AX register

As we discussed above, another name for AX is the accumulator register or accumulator for short, which can be divided into two independent 8-bit registers AH and AL; The AX register is arguably the most frequently used register in assembler programming.

Here are some pieces of assembly code

Mov ax,20 /* insert 20 into register ax */ mov ah,80 /* insert 80 into register ah */ add ax,10 /* add 8 */ to register AXCopy the code

Ax, ah in this code, but in this comment ax, ah is the same, case insensitive.

AX is unique to other general-purpose registers in that it uses DIV and MUL instructions.

DIV is the division instruction in the 8086 CPU.

MUL is the multiplication instruction in the 8086 CPU.

BX register

BX is called a data register, which means it can temporarily store general data. Also to accommodate previous 8-bit cpus, BX can be used as two separate 8-bit registers, namely BH and BL. BX is also used for addressing, finding physical memory addresses, in addition to its ability to hold data temporarily. The data stored in the BX register is usually used as the offset address, because the offset address is of course an offset from the base address. The offset address is stored in the segment register, which we’ll talk about later.

CX register

CX is also a data register and can temporarily store general data. Also to accommodate previous 8-bit cpus, the CX can be used as two independent 8-bit registers, with CH and CL. In addition, CX also has its special uses. The C in CX is translated into Counting function. When using the LOOP instruction in an assembly instruction, you can specify the number of times you need to LOOP through CX. Each time you execute the LOOP, the CPU does two things

  • One thing is that the counter automatically decreases by one

  • The other thing is to determine the value in CX, and if the value in CX is 0 it will break out of the loop and continue executing the instructions below the loop,

    Of course, if the value in CX is not 0, the instruction specified in the loop continues to execute.

DX register

DX is also a data register, which can temporarily store general data. Also in order to accommodate the previous 8-bit cpus, the use of DX was already described in the AX register, which supported MUL and DIV instructions. Value overflow is also supported.

Segment register

The CPU contains four segment registers that are used as base locations for program instructions, data, or stacks. In fact, all references to memory on the IBM PC contain a segment register as the base location.

The segment register mainly contains

  • CS(Code Segment)Code register, the base location of program code
  • DS(Data Segment): Data register, the base position of a variable
  • SS(Stack Segment): stack register, the base position of the stack
  • ES(Extra Segment): other registers, other base locations of variables in memory.

Index register

The index register mainly contains the offset of segment address, and the index register is mainly divided into

  • BP(Base Pointer): Base pointer, which is the offset on the stack register used to locate variables on the stack
  • SP(Stack Pointer): stack pointer, which is the offset on the stack register used to locate the top of the stack
  • SI(Source Index): indexing register, used to copy source strings
  • DI(Destination Index): Target indexing register, used to copy to target string

State and control registers

There are only two registers left, the instruction pointer register and the flag register:

  • IP(Instruction Pointer)Instruction pointer register, which stores the next instruction to be executed from the offset in the Code Segment register
  • FLAGThe: Flag register stores the status of the current process
    • Direction: Indicates the transmission Direction of the data block, whether it is upward or downward
    • Interrupt: 1 – Allowed; 0 to ban
    • Trap: Determines whether the CPU should stop after each instruction is executed. 1 – on, 0 – off
    • Carry: Sets whether the last unsigned arithmetic operation has a Carry
    • Overflow: Sets whether the last signed operation overflows
    • Sign: If the last arithmetic operation is negative, set 1 = negative and 0 = positive
    • Zero: If the result of the last arithmetic operation is Zero, 1 = Zero
    • Auxiliary Carry (Aux Carry) : Used for carrying the third to fourth places
    • Parity: Used for Parity checking

Physical address

As we all know, when the CPU accesses the memory, it needs to know the specific address to access the memory. Memory unit is the basic unit of memory. Each memory unit has a unique address in the memory, which is the physical address. The interaction between CPU and memory has three buses, namely data bus, control bus and address bus.

How does the CPU get its physical address into memory through the address bus? That will be the focus of our discussion.

Now, let’s discuss some of the structural issues related to the 8086 CPU.

Cxuan has talked with you for so long, you should know that the 8086 CPU is a 16-bit CPU. Then, what is a 16-bit CPU?

You’ve probably heard this answer in general, “a 16-bit CPU means that the CPU can process 16 bits of data at a time.” Being able to answer this question means that your bottom line is good, but it’s not comprehensive enough

  • The CPU’s internal arithmetic unit can process up to 16 bits of data at a time

Arithmetic unit is ALU, operation control unit, it is one of the three core components of CPU, mainly responsible for data operation.

  • The register has a maximum width of 16 bits

The maximum width value of this register is the maximum number of binary digits that the universal register can process

  • The path between the register and the arithmetic unit is 16 bits

This refers to the bus between the registers and the arithmetic unit, which can transfer 16 bits of data at a time

Well, now you know why it’s called a 16-bit CPU.

Now that you know the answer to the above question, let’s talk about how to calculate physical addresses.

The 8086 CPU has a 20-bit address bus, and each bus can transmit a bit address, so the 8086 CPU can transmit a 20-bit address, that is, the 8086 CPU can reach the 2^20 power of addressing capacity, that is, 1MB. 8086 CPU is 16 bits structure, from the structure of the 8086 CPU, it can only transmit 16 bits of address, that is, 2^16 power is 64 KB, so how does it achieve 1MB of addressing capacity?

Originally, the 8086 CPU uses the combination of two 16-bit addresses to transmit a 20-bit physical address, as shown in the following figure

Describe the process described above

The related components in the CPU provide two addresses: segment address and offset address. These two addresses are 16 bits. They are converted by the address adder into a 20 bit physical address, which is the physical address passed to memory by the input/output control circuit.

Address adder uses physical address = segment address * 16 + offset address to synthesize physical address from segment address and offset address.

Here’s how the address adder works

The actual segment address * 16 is 4 bits to the left. In the above description, physical address = segment address * 16 + offset address, in fact, is a concrete implementation of the basic address + offset address = physical address addressing mode. The base address is actually the segment address times 16.

You may not be familiar with the concept of a paragraph, so let’s explore it.

What is the period of

The concept of segments is often used in operating systems, such as memory management, where the operating system stores different data segments, such as code segments, data segments, BSS segments, roData segments, and so on.

Cxuan tells you who did it. It was actually made by the Boss CPU behind the scenes. The memory was used as the object of criticism.

In fact, the memory is not segmented, segmented completely by the CPU, the above talk by the base address + offset address = physical address of the physical address of the memory unit, so that we can segmented CPU management.

As is shown in

This is a schematic diagram of two 16 KB programs being loaded into memory. It can be seen that the segment address size of these two programs is 16380.

Note that the segment address of the 8086 CPU is calculated as segment address * 16, so the 16-bit addressing power is 2^16, so the length of a segment is 64 KB.

Segment register

Cxuan just briefly introduced the concept of the segment register for you above, but the introduction is a little shallow, and the introduction of the segment register will not introduce the segment, but also have a feeling of not knowing the truth. Now I will give you a detailed introduction, I believe that after reading the concept of the above segment, the segment register is also easy to grasp.

We mentioned in the composition of the physical address diagram the concept of related parts, which are actually segment registers, namely CS, DS, SS, ES. When the 8086 CPU accesses memory, these four registers provide the segment address of the memory unit.

The CS register

To talk about CS register, then IP register is you can not go around the past. CS and IP are very important registers of the 8086 CPU. They indicate the address where the CPU currently needs to read instructions.

The full name of CS is Code Segment. The full name for IP is Instruction Pointer. Now you know why these two came together!

In an 8086 CPU, the content referred to by CS:IP is executed as an instruction. As shown in the figure below

To illustrate the figure above

In CPU, CS and IP provide segment address, adder is responsible for converting to physical address, I/O control circuit is responsible for input/output data, instruction buffer is responsible for buffer instruction, instruction executor is responsible for executing instruction. A contiguous area of memory in which machine code is stored and addresses and assembly instructions are stored.

In the above picture, the segment address and offset address are 2000 and 0000 respectively. When these two addresses enter the address adder, the address adder converts the two addresses into physical addresses

The address adder is then responsible for conveying instructions to the I/O control circuit

The I/O control circuit sends a 20-bit address bus into memory.

Then fetch the corresponding data, namely B8, 23, 01, in the figure B8, BB are operands.

The control input/output circuit will feed B8 23 01 into the instruction cache.

At this point, the instruction is ready to execute, and the IP, the instruction pointer, is automatically increased. The IP address is the offset address from the Code Segment CS. It knows the address of the next instruction to read, as shown in the figure below

After this, the instruction executes the fetched instruction B8, 23, 01.

And then I’m going to send 2000 and 0003 to the address adder to read the following instructions. The subsequent instruction reading process is exactly the same as what we discussed above, and cXuan will not be repeated here.

From the above description, we can summarize the working process of the 8086 CPU

  • The segment register provides the segment address and offset address to the address adder
  • The address adder calculates the physical address and sends the physical address to memory through the input/output control circuit
  • Extract the instruction corresponding to the physical address, retrieve it through the control circuit and send it to the instruction cache
  • The IP continues to point to the address of the next instruction, while the instruction executor executes the instruction in the instruction buffer

What is Code Segment

Code Segment mov ax,0123H mov Bx, 0003H Mov bx, 0003H We can store a block of code of length N in a block of memory with consecutive addresses that are multiples of 16, and we can think of that as the block of memory where the code is stored.

DS register

When the CPU reads or writes a memory unit, it needs to know the address of the memory unit. In an 8086 CPU, there is a DS register, which is usually used to store the segment address for accessing data. If you want to read 10,000 hours of data, you might need the following code

mov bx,10000H
mov ds,bx
mov a1,[0]
Copy the code

The above three instructions read 10000H into A1.

In the assembly code above, the MOV instruction can be transmitted in two ways

  • One is to send data directly into a register
  • One is to send the contents of one register into another register

But not only that, the MOV instruction also has the following expressions

describe For example,
Mov register, data For example: mov AX,8
Mov register, register Mov AX,bx
Mov register, memory unit Mov ax,[0]
Mov Memory unit, register For example, mov[0], ax
Mov segment register, register For example: MOV DS, AX

The stack

Stack I believe most of you are already familiar with the stack is a storage space with a special access mode. What makes it special is that it enters the stack first and exits it last, which is what we call first in and then out.

It’s like a big drop box, and you can put the same kind of things in it, like books, and the book that goes in the drop box first is at the bottom, and the book that goes in the drop box last is at the top, and if you want to get a book, you have to start at the top, otherwise you can’t get the book at the bottom.

So this is the data structure of the stack, where you push the book into the bin and you take the book out of the bin is called a pop, and it looks something like this

Pushing is equivalent to adding, and pushing is equivalent to deleting, but called differently. Unlike memory, the stack does not need to specify the address of the element. Its general usage is as follows

// Press the data in
Push(123);
Push(456);
Push(789);

// Pop up data
j = Pop();
k = Pop();
l = Pop();
Copy the code

In the stack, LIFO means that the Last In data stored In the stack’s array is read First Out.

Stack and SS register

Here we will use a piece of assembly code to describe the process of pushing the stack into the pop-up

The 8086 CPU provides both PUSH and out instructions, the most basic of which are PUSH and POP. For example, push AX will push data from the AX register onto the stack, pop AX means to take data from the top of the stack and put it into the AX register.

One thing to note here: in the 8086 CPU, both loading and unloading are done on a word basis.

I have an initial stack here, without any instructions or data.

And then when we push the data on the stack, the data on the stack looks like this

The instructions involved are

mov ax,2345H
push ax
Copy the code

Note that the data is stored in two cells, the high address cell for the high 8-bit address and the low address cell for the low 8-bit address.

Push the data on the stack

The instructions involved are

mov bx,0132H
push bx
Copy the code

Now we have two pieces of data in the stack, and now we’re going out of the stack

The instructions involved are

pop ax
/* ax = 0132H */
Copy the code

And then you go ahead and pull out the data

The instructions involved are

pop bx
/* bx = */
Copy the code

The complete push and pop process is shown below

Now Cxuan asks you a question. What we have described above is that 10000H ~ 1000FH space is used as the access unit of push and POP instructions. However, how do you know that the stack unit is 10000H ~ 1000FH? That is, how do you select a specific stack unit to access?

In fact, the 8086 CPU has a set of stacks of registers, SS and SP. SS is the segment register, which stores the base position of the stack, i.e. the position at the top of the stack, while SP is the stack pointer, which stores the offset address. At any given moment, SS:SP points to the top element of the stack. When the push and POP instructions are executed, the CPU gets the address at the top of the stack from SS and SP.

Now, we can describe the process of push and POP completely. Cxuan will give you a derivation of the process.

The key changes involved in the above process are as follows.

SP = sp-1 when a byte unit is pushed onto the stack using the PUSH instruction; The top element of the stack changes;

SP = sp-2 when PUSH is used to PUSH a 2-byte word unit onto the stack; Even the top element of the stack changes;

SP = SP + 1 when a byte unit is popped from the stack with the POP instruction; The top element of the stack changes;

SP = SP + 2 when a 2-byte unit of word is popped from the stack using the POP instruction; The top element of the stack changes;

Stack top out of bounds problem

Now we know that the 8086 CPU can use SS and SP to indicate the location of the top of the stack, and provide PUSH and POP instructions for pushing and removing the stack. So, you know how to find the top of the stack, but how do you ensure that the top of the stack is not out of bounds? What happens when the top of the stack goes out of bounds?

For example, here is a schematic diagram of a stack top out of bounds

At first, the SS:SP register points to the top of the stack, and then pushes a certain number of elements to the stack space. SS:SP is located at the top of the stack space, and then pushes elements to the inside of the stack space, and the problem of the top crossing will occur.

Overstepping the top of the stack is dangerous, because if we arrange an area of space as a stack, we may store other instructions and data outside of the stack space, which may belong to other programs, and thus confuse the computer.

We want the 8086 CPU to solve the problem by itself, after all, the 8086 CPU is a mature CPU, to learn to solve the problem by itself.

The 8086 CPU will tell you where the top of the stack is, not how big the stack space is, so you need to manually ensure that the 8086 CPU will tell you where the top of the stack is.

In addition, I have exported six PDFS, which are available for free download, as shown below

Link: pan.baidu.com/s/1mYAeS9hI… Password: p9rs