Today I officially start my interview journey. Due to my own work experience, I seldom use JUC-related treatment at ordinary times. Today although also asked, with their own experience of reading a few books barely pass, as the bounty of the subtext, good luck does not favor fools. Today’s interview questions are Volatile and Synchrnized.

Uphold the physical education teacher taught us Lu Xun said: sensitive and studious, not to read a book. As PE students who never skip class, certainly listen to the teacher’s words, we will open this window.

We won’t go over the MEMORY model of the JVM, but look at my previous post on this blog. What does the CPU Cache model look like?

L1, L2, and L3, we won’t draw it, it doesn’t matter. Why is there a third party Cache between CPU and RAM? Here not for CPU flower heart, but in order to solve the low efficiency of CPU to directly access memory, the application in the process of running, the operation will be the required data from main memory to Copy a to the Cache, so the CPU to calculate can directly to read and write data in the Cache, when after the operation, After the Cache is added to the main memory, the CPU accesses the Cache instead of main memory directly. Greatly improved CPU throughput capacity.

There is a minor third between CPU and main memory, how to solve the CPU cache consistency problem?

  • Read I from main memory into CPU Cache
  • Add one to I
  • Write the result back to the CPU Cache
  • Flush data to main memory

In this scenario, two threads are operating at the same time and I starts at 0, so it increments twice and results in a 1. It should actually be 2.

  • The bus lock
  • Cache consistency protocol

Bus lock is too pessimistic, I bought an 8-core CPU in multi-threading under you insist that I use a single-core, my money is not wind, how can use it.

Cache consistency is best known for Inter’s MESI protocol. The MESI protocol ensures that each Cache has a consistent copy of a shared variable. The general idea is that if a CPU is operating on a Cache and the variable is found to be a shared variable, the CPU Cache also has a copy that does the following

  • A read operation reads data from the Cache into a register without doing any processing.
  • Write operation, which signals other cpus to set the variable’s Cache line to invalid state, forcing other cpus to fetch the variable again from main memory.

Saturday in the yard to continue