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Overview of CSM300

CSM300(A) series is A CAN module that CAN support SPI/UART interface.

1. Introduction

CSM300(A) series isolated SPI/UART to CAN module is integrated microprocessor, CAN transceiver, DC-DC isolated power supply, signal isolation in one communication module, the chip CAN be easily embedded in the device with SPI or UART interface. Without changing the original hardware structure, the device CAN obtain the CAN communication interface to realize the data communication between SPI device or UART device and CAN bus network.

appearance

Parameters of 2.

  1. Realize SPI or UART and CAN interface two-way data communication;
  2. CAN bus conforms to ISO 11898-2 standard;
  3. It integrates one SPI interface and supports user-defined rates up to 1.5Mbit/s (non-custom protocol conversion) or 1Mbit/s (custom protocol conversion).
  4. Integrated 1 UART interface, support various rates, up to 921600bps;
  5. Integrated 1 CAN communication interface, supporting a variety of baud rates, up to 1Mbps;
  6. Isolated pressure withstand 2500VDC;
  7. Operating temperature: -40℃~+85℃;
  8. The electromagnetic radiation EME is low;
  9. EMS is high;

As shown in the figure above, CSM300 is 5V and CSM300A is 3.3V.

If the working voltage of MCU and MPU is not 1.8V for so long, a level Shift should be added for voltage conversion.

The board used for this debugging is CSM300A, and only the SPI interface is used.

3. Pin definition and reference circuit

When using the SPI to CAN function, the MODE pin needs to be connected to a high level. The SPI interface of MCU is connected with the SPI interface of CSM300(A). Meanwhile, MCU needs to provide GPIO with pin connections of RST, INT, CTL0 and CTL1 to realize effective monitoring and control of CSM300(A). If CSM300(A) needs to be configured through MCU, additional GPIO to CFG pin connection is required.

Pin description:

Pin functions are described as follows:

  1. MODE pin is directly connected to high voltage (high level corresponds to SPI MODE, low level corresponds to UART MODE);
  2. 10, 11, 12 external CAN bus, mainly used for CAN communication;
  3. Pins 3, 6, 7, 24 and 19 are connected to MCU/MPU. The mode and read/write operation of CSM300A depend on these pins.
  4. The four pins 18, 21, 22 and 23 need to be connected to the SPI controller pins of MCU/MPU, which are mainly the SPI channels for sending configuration information and reading and writing data on the CPU side.
  5. 20 is an INT pin. After CSM300A receives data and meets certain conditions, it will pull down this pin to generate an interrupt signal and notify the CPU to read data.

Ii. Working mode

1. Classification of working modes

After the CSM300(A) is powered on, the MODE and CFG pin levels determine that the product is in one of four different operating modes: SPI to CAN MODE, UART to CAN MODE, SPI configuration MODE, and UART configuration MODE.

As shown in the above table:

  1. If we want to configure CSM300A, that is, to set the CSM300A MODE to SPI configuration MODE, then we need to set the MODE pin to 1, CFG to 0, RST to 1;
  2. If we want to read and write data through CSM300A, that is, to set the CSM300A MODE to SPI MODE to CAN MODE, then need to set the MODE pin to 1, CFG to 1, RST to 1;
  3. Data read and write operations belong to SPI to CAN mode, and there is no need to switch mode.
  4. If you need to switch the working mode of the product, after changing the pin level, you must reset the product to make it enter the setting

Fixed working mode. Note that to ensure a successful reset, the retention time is at least 100us. After the reset, the waiting time for product initialization is at least 3ms. Operations can be performed only after the product initialization is complete.

Below is a sequence diagram for switching between different modes.

2. SPI to CAN mode (data read and write)

In this working mode, CSM300(A) always acts as SPI slave, SPI is limited to work in mode 3 (CPOL and CPHA are both 1), data length is limited to 8 bits, and MSB is transmitted first. The maximum communication rate is 1.5 Mbit/s under transparent conversion and PBT, and the maximum communication rate is 1 Mbit/s under user-defined protocol conversion.

The SPI host CAN send data to and receive data received by the CAN bus. In this case, the UART interface is invalid and does not process any data on the UART interface or return the data received by the CAN bus to the UART.

  1. SPI frame

SPI data between a chip selection is valid and a chip selection is invalid is defined as one frame of data. There should be a 40us interval between reading and writing buffer data from frame to frame.

3. SPI configuration mode

In this mode, the CSM300(A) is waiting for configuration and cannot send or receive data to the CAN terminal. In this mode, you can configure only through the SPI interface.

Three, host control

The CSM300(A) has two SPI host control pins, CTL0 and CTL1, which are controlled by the host. By controlling the pins of CTL0 and CTL1, the host makes CSM300(A) enter different functional states to achieve different operation purposes for CSM300(A). The corresponding functions of different host control pin levels are shown in the following table:

The host obtains the number of bytes that can be read and written by reading the current status of the slave machine. The host selects the function as host read state, and then reads 4 bytes through SPI, which is the status code. The status code consists of 32 bits. The following table describes the specific definitions.If the status[] array is defined as an 8-bit integer, and the data read successively through SPI reading states are status[0], status[1], status[2], and status[3], the data structure is shown as follows:

Iv. Feedback Mechanism (interruption)

The CSM300(A) CAN only act as an SPI slave and cannot actively control other SPI bus devices, so if A CAN data frame is received, it must be actively returned to the CPU side.

The INT feedback pin on the hardware of CSM300(A), which is connected to the host. In the following two cases, the INT pin will change from high level to low level to inform the host to read data (in order to avoid data loss, it is recommended that the host use low level trigger detection mode) :

  1. CAN buffer When the number of CAN frames reaches the set trigger point

When the number of CAN frames received by the product CAN bus receiving buffer reaches the trigger point, the INT pin level is set low, and the INT pin level will not return to high until the buffer is cleared. The user CAN query the status of CSM300(A) after getting the INT signal, get the number of bytes readable, and then read the buffer CAN data.

  1. CAN buffer data is less than the number of trigger frames, and the host has not read within the set time

When the CAN buffer has data but less than the number of trigger frames, if the bus does not add data for a long time and the host does not perform read operation, the data received by the CAN buffer may not be processed for a long time, which results in poor real-time performance of data. In order to solve the real-time problem of A small amount of data, CSM300(A) has A timer set internally. If the data in the CAN buffer is not read within A certain period of time, the INT pin will be set low to notify the host to read the data. CSM300(A) When the last frame of data is received, the timer starts and the host resets the timer when the read operation is performed.

5. Networking mode

CAN bus generally uses linear wiring, and the number of bus nodes CAN reach 110. Shielded twisted pair cables are recommended for cabling. CANH and CANL are connected to the core of the twisted pair cables, CGND is connected to the shield layer, and the shield layer is grounded at a single point.

Thanks to the CSM300(A) minimum baud rate of 5kbps, the bus has A maximum communication distance of 10km.

Six, transplant

1. Hardware connection diagram

As shown above:

  1. SPI controller has been integrated on SOC, and the SDK of the manufacturer has included the device tree and driver information of SPI controller;
  2. The SPI controller pin of SOC needs to be connected with Level Shift first for voltage boost. The board voltage is 1.8V, while the CSM300 requires a voltage of 3.3V.
  3. GPIO 76/107/113/114 of SOC connects to RST/CFG/CTL1/CTL0 of CSM300A respectively through level Shift;
  4. Running can-test software on PC CAN read and send data from CAN bus through USB to CAN device.

[Note] USB to CAN device, CAN search by itself, eliminate advertising.

2. The device tree

Here is the official device tree:

csm300@0 {
	pinctrl-names = "default";
	pinctrl0 =<&pinctrl_csm300>;
	gpios=<&gpio3 21 0    /*ctl0*/
		&gpio3 22 0 /*ctl1*/
		&gpio3 30 0 /*rst*/
		&gpio3 31 0 /*cfg*/
	>;
	interrupt-parent = <&gpio3>;
	interrupts = <26 IRQ_LEVEL_LOW>;
	compatible = "zhiyuan,csm300";
	spi-max-frequency = <500000>;
	reg = <1>;
	status = "okay";
};
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The following is based on the results of their own platform, readers need to transplant according to their own platform, not dogmatic.

csm300@0 {
	pinctrl-names = "default";
	gpios=<&gpio 114 0    /*ctl0*/
		&gpio 113 0 /*ctl1*/
		&gpio 76 0 /*rst*/
		&gpio 107 0 /*cfg*/
	>;
	interrupt-parent = <&gpio>;
	interrupts = <196 IRQ_LEVEL_LOW>;
	compatible = "zhiyuan,csm300";
	spi-max-frequency = <500000>;
	reg = <0>;
	status = "okay";
};
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3. The driver

The official driver cSM300. c will be provided. The specific and practical principle will not be discussed in this paper.

Copy to the following directory:

drivers/net/can/spi
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Modify the Makefile in this directory

 obj-$(CONFIG_CAN_CSM300)	+= csm300.o
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Modify Kconfig in the local directory

config CAN_CSM300
	tristate "Microchip CSM300 driver"
	depends on SPI 
	---help---
	  Driver for the Microchip CSM300  .
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Run make Menuconfig. The driver location is as follows:Select the driver:

Recompile the kernel.

Note: This driver also relies on CAN and SPI, which must be selected.

4. Add debugging interfaces

The CSM300 driver fails to register successfully for various reasons during debugging. How to determine whether the SPI controller driver is faulty or the CSM300 driver is faulty?

In order to facilitate through spi controller sends a waveform, we add the following code, for use in the board directory/sys/bus/spi/drivers/csm300 created in the state file node, through writing different values to generate the spi data, Or control RST, CFG, CTL0, CTL1 pins.

  1. Add function csm300_spi_store()

** check_cSM300 ()** is the driver’s own function used to test the SPI communication function of the CSM300.

This function first sets the CSM300A to SPI configuration mode, then writes 9 data, and then reads and retrieves the data to verify that the data is correct.

  1. Modify probe function
struct net_device *global_net = NULL; Csm_probe () {... global_net = net; ret = check_csm300(net); ... ret = driver_create_file(&(csm300_can_driver.driver),&driver_attr_state);if(ret < 0){
		ret = -ENOENT;
		goto out_free;
	}
	……
}
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  1. The test command

The CSM300 module directory is displayed

cd /sys/bus/spi/drivers/csm300
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  1. Generate SPI data
echo 3 > state
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  1. Example Expand RST, CFG, CTL0, and CTL1
echo 1 > state
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  1. Lower RST, CFG, CTL0, and CTL1
echo 0 > state
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5. Correct boot log and waveform

After startup, the driver will call check_cSM300 () to test the SPI channel, sending data asF7: F8:02… The following is the waveform of the CLK and MOSI pins of the SPI interface:You can see that the data is consistent with what we sent.

6. Waveform diagram of received data

The steps for receiving data are as follows:

  1. CAN Test software running on PC sends data 00 01 02 03 04 05 06 07,
  2. After passing through the USB to CAN device, it is converted into differential signal,
  3. After arriving at CSM300A, the signal is modulated to a square wave,
  4. CSM300A sends an interrupt signal to the CPU by pulling down pin INT, calls the interrupt function registered by CSM300A,
  5. The CSM300A interrupt program running on the CPU reads data from the CSM300A through the SPI interface.
  6. After CSM300A buffer data is read, raise INT,
  7. The driver passes the received data up to the application layer, and the CANDump command gets the CAN frame data.

The data sending process is similar to the above procedure.

7. CAN command

If the can command does not exist in the file system, you need to transplant it.

1) Set the baud rate and enable the CAN0 port

ip link set can0 up type can bitrate 800000
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2) Send data

cansend can0 1F334455 #1122334455667788
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3) View the received data

candump can0
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Seven, error records

A lot of errors were encountered during the debugging process, and CSM300A located the problem steps:

  1. Firstly, oscilloscope is used to test the waveform of THE MOSI pin of CSM300 to see if it is consistent with the waveform in Section 5 of Chapter 7. If it is inconsistent, it indicates that the SPI controller driver is not loaded correctly.
  2. To generate data through the SPI controller, use the command echo 3 > state;
  3. If the waveform is consistent, measure the four pins RST, CFG, CTL0, CTL1 to check whether the level is correct;
  4. To check whether the control of RST, CFG, CTL0, and CTL1 is correct, run echo 0 > state and echo 1 > state to lower and raise the control of these pins.

Basically follow this idea to debug quickly can locate the problem.

The following is the log of the driver loading error. The main reason of the error is that the check_cSM300 () function is called to write data to CSM300A and then read out data mismatch, so as to determine the loading error.

1. The CFG pin is abnormally pulled down

The check_cSM300 () function always returns an error.

Analysis: Check failed, basically because SPI controller and CSM300 communication problems. First, use oscilloscope to check whether the data sent by SPI normally reaches CSM300 (grab SSEL, CLK, MOSI with oscilloscope), and the result is normal.

So the detection of RST, CFG, CTL0, CTL1 four pins. As shown in the following figure, use echo 0 > state to pull down the CFG pin and find that it does not pull down to 0V.Solution:

Leave it to the hardware engineers. This brother to CFG added a reverse resistance, the driver part of the need to set all CFG code, all inverted.

gpio_set_value(priv->CFG,0); Modified into gpio_set_value (priv - > RST,1);
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gpio_set_value(priv->CFG,1); Modified into gpio_set_value (priv - > RST,0);
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2. The RST delay is insufficient

Echo 0 > state can be lowered and the measurement is correct, but CSM300 is still unable to receive data frames.

Analysis: General data cannot be received, there are two possibilities: the INTERRUPT signal given by CSM300 is not intercepted by CPU, and CSM300 is not in SPI to CAN mode.

Firstly, oscilloscope was used to confirm that the data from USB to CAN had successfully reached CSM300, so the corresponding pin levels RST, CFG, CTL0 and CTL1 were detected and found to be correct.

Check the interrupt count. Run cat /proc/interrupts to check whether the CSM300 has an interrupt count.

It was suspected that CSM300 did not have RST successfully, so it executed echo 3 > state to check whether RST was set correctly, and the result found the following waveform. It was confirmed that the pin was pulled up slowly, so CSM300 could not sample this level.

Change method: Increase the delay time for each RST operation in the driver:

gpio_set_value(priv->RST,0);
usleep_range(2000.2300);
gpio_set_value(priv->RST,1);
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After the modification, run echo 3 > state. The RST waveform is shown as follows.

Official download www.zlg.cn/index.php/p…