The articles

Look for similar pictures in IOS album NSNotification and class object, instance object icloud-Documents store CocoaPods private source build CPU fetch decoding execution

start

Last time we looked at how a simple assembly language command can be converted into a CPU instruction, and how the CPU can fetch the specified instruction in memory and load it into the control unit to perform a fetch and decode operation. Please click here

Again, let’s use a simple CPU architecture diagram to explain what absolute CPU addressing is

Refer to my last article for the names of the various components in this diagram

Assembly instruction

LD A,(EC00H)

Copy the code

The above assembly instruction means that register A loads the 8-bit binary data of A particular memory address (NN). The special feature is that the address of the octet is also part of the instruction.

EC00 represents the address of the octet binary in memory. LD A means load with register A

Absolute addressing process

LD A,(EC00H) This instruction is represented in the figure as follows

3A indicates the hexadecimal form of the LD A command

EC00 represents the memory address of the data to be manipulated

4B indicates the hexadecimal format of the data to be operated on

opcode

Where LD A stands for the opcode, the CPU instruction that needs to be executed, commonly known as Opcode

The operand

EC00H is also an instruction that needs to be executed by the CPU, called an operand, usually called an operand.

By observing the relationship between the operand and the data to be operated on (4B), we can see that the operand is the memory address EC00 of the data to be operated on (4B).

In memory address EC00 is stored in two contiguous memory. 00 in AE01 and EC in AE02 respectively.

Generally we call 00 stored in AE01 the low byte of the data address.

EC in AE02 is the high byte of the data address.

Execute 3A command

First, the PC(program counter) in our CPU reads the address AE00 of instruction 3A. Then through the address bus to select AE00 3 a instruction, then the control unit reads the command control, through the control bus will read the instructions to the memory, this time through the data bus, memory will 3 a instructions to the BR register (cache), then rush in the buffer register copy to the IR () in the instruction register, after a decoder to decode, Put the control unit in and let the CPU know what to do next in ten seconds. See our last article for an implementation

The process is shown below

Get data address

Gets the 00 low byte address

When the CPU loads the 3A instruction into the CU(control unit), it means that the CPU has acquired the opcode. The next step is to retrieve the operand, which is the memory address of the 4B data that needs to be retrieved.

After completing the 3A instruction read above, the PC(program controller) grows once to point to the next memory address AE01, then MAR(address register) selects the AE01 address in memory through the control bus, and CU (control unit) sends the read instruction to memory through the control bus. Then the memory will address AE01 content 00 through the data bus into the BR buffer register for temporary storage.

The process is shown below

Get the EC high byte address

Now that the low byte address 00 of 4B has been successfully obtained and put into BR (buffer register), the high byte address EC is just short of the full address EC00 of 4B. So our PC(program counter) still has to do its job, pointing to the next address AE02 with the high EC, and putting the contents of address AE02 into the BR(buffer register) through the data bus. Concatenate the low byte 00 that was previously put into the BR(buffer register) with the high byte EC that was just fetched. So now we have the complete data the address of 4B.

The flow chart is shown below

Load the data

After the above addressing operation we can get the complete address of data 4B (EC00), we copy the complete address of data 4B (EC00) from BR(buffer register) into MAR(address register), and select the address that holds 4B data EC00. The control unit then sends the read instructions to the memory through the control bus, and the memory sends the data 4B in the EC00 address to the cache register through the data bus. Data 4B is then copied from the buffer register to register A, thus completing an absolute addressing of the data.

The flow chart is as follows

conclusion

The drawing is a little rough, please bear with me. If there are any mistakes in the above article, please comment below and I will correct them in time