Most of the content from the Peking University course computer composition, speaking is really too good!
Events encountered by the CPU
In today’s increasingly powerful computers, the CPU may encounter a series of special events during its execution. For example, divisor 0, result overflow, I/O device interrupt, and so on.
For these events, our processing process is generally as follows:
- When a program is running, an “event” occurs outside the system, inside the system, or within the current program itself that requires special handling.
- The CPU immediately forcibly stops the current program, changes the working state of the machine, and starts the corresponding program to handle these “events”.
- After the processing is complete, the CPU resumes the original program.
Take result overflow as an example, the HARDWARE circuit of CPU is very easy to detect result overflow, but the problem is to detect overflow how to do?
One approach is to handle overflow entirely with hardware circuitry, which is obviously not flexible enough. Once the CPU is made, the circuit is fixed and we can’t change it. There is no way to change the way the overflow is handled.
In addition, when a new type of interrupt occurs, the computer will not be able to handle it correctly because the circuit is already fixed.
So it’s best to use software to solve it.
Ideas for handling particular “events”
Modern computers use an interrupt vector table to deal with interrupts.
The interrupt direction scale, as the name implies, is a table. The diagram below:
The hexadecimal number on the left is the address, and the box on the right is the contents of the interrupt vector table. Each of these four squares forms an interrupt vector, a total of four bytes (the same colored box in the figure represents an interrupt vector).
This interrupt vector table is initialized at system startup (in real mode) and stored in a fixed area of memory (for example, the 8086CPU stores the interrupt vector table at the lowest 1KB, holding 256 interrupt vectors). Therefore, when the system receives the interrupt signal, the memory access can be issued directly through the circuit Settings to read the content of an interrupt vector. In an 8086CPU, the higher two bytes are sent to the CS register and the lower two bytes are sent to the IP register (the 8086 uses CS:IP to determine the address of the next instruction). Then the next cycle the CPU will fetch instructions from that address. We already have a handler to handle the interrupt in place of this address, so the interrupt will be handled.
This method is very extensible and flexible. When a new interrupt is added, we only need to write the interrupt handler and initialize the new interrupt direction table. And when we want to modify the processing method, we can directly modify the interrupt handler, without changing the original hardware circuit. See the power of software’s methods!
Interrupt to scale development
Take 8086 as an example:
1. With the development of CPU, the content of interrupt direction table began to increase, 8086 has 5 interrupts.
2. With the development of CPUS, most cpus run in protected mode (you can search on the Internet for the difference between real mode and protected mode).
The addressing of the instruction changes in different modes:
- Through CS:IP in real mode
- In protected mode, use CS:EIP
EIP is a 32-bit register, with the lower 16 bits representing IP, which is for upward compatibility.
In protected mode, the segment base address is no longer in CS, but in memory. Somewhere in memory, there is a table called a segment descriptor table (a table is an array). This table has a total of 2^16=8192 entries, each consisting of 8 bytes, called a segment descriptor.
As you can see, 2,3,4,7 bytes represent the base address, which corresponds to the address stored in CS in real mode. The segment boundary specifies the length of the segment, and the permission specifies whether the segment can be read or written.
The base address of this memory region is in GDTR (Global Descriptor register). This table is created in real mode and gives the base address to GDTR. GDTR can then be used to locate the base address of the table, and then the CS register can be used to locate a descriptor (CS is 16 bits and can address 8192 memory units, just enough to be an offset).
3. In the protected mode, the position of the interrupt vector table changes.
The interrupt vector table is no longer stored at the beginning of address 0, but can be stored at any location. The name also becomes the interrupt descriptor table.
In fact, it is similar to the real mode above. But here we need IDTR (interrupt Descriptor table register) to hold the base address of this table.
Bytes 0,1,7,6 correspond to EIP. The segment selector will be placed in CS, and the segment base address to extract the segment descriptor will be found by GDTR:CS. The segment base address :EIP is then used to find the corresponding interrupt handler entry address.
The next article will show you the process of interrupt handling.