** Abstract: ** I believe that everyone is very familiar with bear’s NB-iot communication expansion board, but have you really understood its internal structure? Today xiaobian don’t talk about technology, take you to do a disassembly · machine · guest!

I believe you are familiar with bear’s NB-iot communication expansion board, but have you really understood its internal structure? Today xiaobian don’t talk about technology, take you to do a disassembly · machine · guest!

Dismantlement object: BC35-G communication module

Bc35-g module is an NB-iot communication module released by CYUAN based on the Hisi Hi2115 (also known as Boudica150) chip. The BC35-G supports the nB-iot +MCU mode and OpenCPU mode.

Nb-iot +MCU mode is a common combination mode (bear IoT is such a combination mode). MCU is used as the main control for data acquisition and control, and MCU sends AT commands to the module to realize data interaction between the device and the Internet. OpenCPU uses the module’s own processing power to complete the WORK of MCU, thus eliminating MCU.

Let’s take off its coat and look inside

Today’s hero is that the largest chip: **Hi2115, ** next xiaobian on this NB-iot chip in-depth analysis.

Hi2115 is the second NB-iot communication chip developed by Huawei Hisi (the first is Hi2110). It has a main frequency of 48MHz, 352KB Flash, 64KB RAM, and supports 3GPP R14 standard. It works in the frequency range of 698-960 MHz and 1695-2180 MHz. The system bandwidth is 200 kHz.

Next, from the shallow to the deep, through the appearance of this chip to explore its deepest “secret”.

The Hi2115 chip has three processor subsystems to separate different functions, facilitate authentication and simplify third-party application development.

Hi2115 chip internal structure block diagram

The three processor subsystems of Hi2115 chip are:

1. Application core processor: The Application core supports users to execute third-party Application code on the Application program

2. Security Core processor: The Security Core maintains the Security and integrity of Hi2115 by verifying the code running on the system. It also generates random numbers and controls the memory access of the other two cores.

3. Protocol Core: The Protocol Core acts as a communication processor and forms the basis of all layers of the communication Protocol stack. It includes a dedicated ARM Cortex M0 core and a Dual-Mac DSP with dedicated on-chip RAM. There is a USIM interface to allow operation with the external SIM, and a MIPI RFFE interface to connect with the external RF circuit interface.

Data is shared among three sub-processors through memory sharing. Each core operates independently, with no interference from the other. Application approval can be trusted to open all user permissions for user side APP development.

The Hi2115 chip has three operating modes, which define the functions available at different levels of power saving.

1. Active Mode

In this mode, all functions of the chip are available and all processors are running normally. Radio transmission and reception are performed in this mode. At the same time, standby mode and deep sleep mode can only be switched between active mode.

2. Standby mode

In standby mode, all processors are inactive, but all peripherals (including DMA and embedded Flash) are active. The system clock is active and power consumption is reduced by clock gating and power gating. Enter standby mode when all processors execute wait interrupt (WFI) instructions.

3. Deep-sleep

Only 32.768kHz RTC and some peripherals operate in this mode. The chip can wake up modules in deep sleep mode by sending messages via RTC interrupts or external events from peripherals. This mode requires all processor inputs to be set to deep sleep mode to enter and then execute wait interrupt (WFI) instructions.

After exploring the framework, let’s specifically understand the peripheral part of Hi2115 chip:

  • 1 universal UART (up to 1.5Mbit/s)
  • 2 low power UART (support asynchronous operation in low power)
  • Two Iics (up to 1Mbit/s)
  • 2 spis (up to 24Mbit/s)
  • 1 10bit ADC (818 KSPS)
  • A 10 bit DAC
  • 1 high speed analog comparator
  • 22 programmable IO (configurable)

Of the 40 PIO of Hi2115 chip, 24 PIO are available on the application core. Each PIO IO pin function is controlled by software, including orientation, interrupt configuration, drive strength, and integrated pull-up and pull-down resistors.

After understanding these, there is a kind of cloud to see the moon feeling?Let’s continue with this feelingThe internal architecture of a chip.

  • Chip power Supply Hi2115 chip is powered by a single power supply, dual mode (PWM/PFM) step-down regulator SMPSU power for the digital core and optimized for deep sleep current. Integrated linear regulators provide analog and radio power tracks for high transmission power and isolation of noise interferers. These linear regulators are powered by a second on-chip SMPSU to improve power efficiency, and to reduce power consumption, the chip can automatically disable the internal radio power track.
  • The reference clock Hi2115 requires a low phase noise reference clock to provide a frequency reference for PLL and ADC, and the chip also requires a 32.768khz crystal oscillator for timing and deep sleep awakening. The processor is driven by an internally generated clock and does not rely on two reference clocks for startup.
  • Radio frequency (rf) function

The Hi2115 chip’s radio is used for NB-iot communications at cellular frequencies. There are two differential LNA inputs with 100 ω impedance that can be configured externally for LB (low band 698-960 MHz) and MB (medium band 1695-2180 MHz). The transmitter has two single-ended outputs with an impedance of 50 ω, one for LB and the other for MB.

There are the following components between the rf port of the transceiver and the antenna:

TX power amplifier

This is a PA capable of producing 23 dBm output power, with a gain of 20-30 dB and enough linearity to meet 3GPP requirements.

2.TX harmonic filter

The specification depends on the choice of PA. In some cases, it may be integrated into the PA and does not need to be used on its own.

3. The TX/RX switch

The RF switch connects the antenna to the PA output and RX input. This switch can be controlled by one or more PIO of Hi2115.

4.RX harmonic filter

A device for filtering out one or more harmonics in a power system

5.RX matching components/Barron

The Hi2115 chip also supports MIPI RFFE interfaces V1.0 and V2.0, which are used to control power amplifiers and RF front-end modules that support 1.8V interfaces and support SCLK frequencies ranging from 32kHz to 26MHz.

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