medium-length

Always remember

• CPU:Central Processing UnitCentral processing unit
• ALU: Arithmetic Logic UnitArithmetic logic unit
• PC: Program CounterProgram counter
• IR: Instruction RegisterInstruction register
• MAR: Memory Address RegisterMemory address register
• MDR: Memory Data RegisterMemory data register

classification

• System software: refers to system programs, mainly operating systems, etc
• Applications: Applications

Von Neumann Computer

• Five parts: arithmetic unit, memory unit, controller, input device, output device
• Instruction and data are placed equally in storage and can be sought by address
• Instructions and data are represented in binary
• Instruction = opcode + address code
• Instructions are sequentially stored in memory
• The machine revolves around an arithmetic unit

Main technical indicators

• Machine word length: The number of bits of data that the CPU can process at a time, usually related to the CPU register number.
• Storage capacity: main storage capacity and auxiliary storage capacity
• Computing speed: It is now commonly used to measure the average number of commands executed per unit of time

The bus

• Bus: The bus is the information transmission line connecting all components, and is the transmission medium shared by all components
• Bus bandwidth: The maximum number of bytes per second that the bus can transfer
• Bus multiplexing; Address bus and data bus reuse the same physical line, time-sharing transmission

Three bus structure computer

IO bus + main memory bus +DMA bus (a bus for exchanging information between IO devices and main memory)

Bus centralization optimization method

The master has control over the bus, and the slave responds to bus instructions sent from the master. The main module sends a request before communication, and only a pair of modules are allowed to communicate at the same time. The bus controller determines which module is preferred. Mainly divided into centralized and distributed.

The centralized

Chain query

• Idea: The bus allows BG to be sequentially passed down from the first part until it reaches the first part where the request is needed (list traversal)
• Advantages: only need a few lines can be in accordance with a certain priority order bus control, easy to expand
• Disadvantages: very sensitive to the fault of the query chain, and the priority of the query is fixed

Counter timing query

• Idea: THE BR line sends a request, the arbiter receives it and counts an agreed interface number value under BS 0, and sends it to each device through the address line. The device address of the interface identifies the line and the value of the count, and sets it as BS 1. At the same time, the device obtains the right to use (array traversal).
• Advantages: Increase counter, priority order can be changed. Low sensitivity to query chain failure
• Disadvantages: increased the number of control lines (equipment address line), control is also more complex (counter)

Independent request

• Idea: Each device and bus mediator has a unique pair of request lines and authorization lines.
• Advantages: Fast response. Flexible prioritization control and the ability to mask requests from invalid devices.
• Disadvantages: the number of control lines, bus control complex.

Bus communication mode

• Various parts of the bus, time-sharing use of the bus
• Bus transmission cycle: the time it takes for a part connected to the bus to complete a complete and reliable transmission of information
  • Application allocation: master module application, bus arbitration decision
  • Addressing: The master module gives addresses and commands to slave modules
  • Data transfer: master module and slave module exchange data, runoff data bus to the destination module
  • End: The main module revokes the relevant information and cedes the right to use the bus
• Bus communication control: to solve the problem of how to know the beginning and end of transmission and how to coordinate the two sides.
  • Synchronous communication: byUnified time scaleControl data transmission
  • Asynchronous communication: YesAnswer modeThere is no common clock standard
  • Semi-synchronous communication: synchronous and asynchronous combination
  • Separated communication: Fully exploit the potential of the system bus at every moment

Synchronous versus asynchronous communication

• synchronous
  • Advantages: clear and unified provisions, modules and simple, consistent pace
  • Disadvantages: Rigid deadlines for all modules, so lack of flexibility
  • Applicable: The clock frequency needs to accommodate the needs of the longest latency and slowest interface on the bus. It is generally used for the occasion where the bus length is short and the access time of each component is similar.
• asynchronous
  • Advantages: Transmission process without strict time requirements, flexibility
  • Disadvantages: the control mode is complex, the cost increases
  • Application: for the transmission of two parts or equipment whose working speed is very different

memory

Related concepts and Definitions

classification

• Access mode
  • Random access (access time and address independent) : RAM; Read only memory ROM;
  • Serial access (time and address friends) : traversing access to memory
• According to the function points
  • Buffer memory: buffer between CPU and main memory
  • Main memory: Exchanges information with the CPU
  • Secondary memory: cannot exchange information directly with the CPU

hierarchy

indicators

• Memory word length: the binary number of a single data unit in the MDR memory data register
• Storage capacity: The total number of bits of binary code in main memory
  • Storage capacity = Number of storage units x Storage word length (MAR x MDR)
  • In bytes divided by 8
• Addressing space: Bytes (1B=8 bits) are the smallest unit of storage, and each address bus 01 indicates that a storage space of 2B size can be addressed. The address space of the root address bus is 2B^n.2^10*bit=1kbit=1024bit=1/8KB
• Access time: Access time to memory (read time/write time)
• 3. The minimum interval between two consecutive independent memory operations (read cycle/write cycle).
• Access cycle > Access time

Dynamic RAM refresh

Relevant concepts

• RAM:Random Access MemoryRandom access memory
• ROM:Read-Only MemoryRead only memory
• DRAM: Dynamic random access memory
• SRAM: Static random access memory

Why refresh

• The essence is to read out the original information, form the original information by the refresh amplifier and write the process of regeneration
• Because storage units are accessed randomly, information on some units that are not accessed for a long time gradually disappears. Therefore, you need to periodically refresh storage units.

Refresh the way

• Periodic refresh: all basic DRAM units must be refreshed once within a certain period of time. Generally, the value is 2ms
• Centralized refresh: Refresh all storage units in a specified period of time row by row.
  • Stop reading and writing on refresh (inefficient dead zone)
• Distributed refresh: The refresh of each row is distributed over each access cycle
  • Access cycle = Read/write or maintain time + refresh time
  • There are no read and write dead zones, but the access cycle becomes longer and the overall system speed decreases
• Asynchronous refresh:
  • Divide the flushes of each row evenly into 2ms, which does all the flushes but reduces the dead time per row to 1/n.

parity

• Idea: It is used to verify the correctness of code transmission, and it is agreed in advance to use odd check or even check. Add a parity bit of 1/0 to the last bit of the sent data set. The receiver verifies whether the number of 1s in all data sets is odd or even. If the number of 1s meets the convention, the parity succeeds.
• Advantages: simple coding and inspection + high coding efficiency
• Disadvantages: can’t detect even number of errors, unreliable conclusion + can’t locate errors, no error correction ability

Progress logging: Follow the intermediate memory extension technology