CPU based

The CPU, or processor, is the circuit that controls the manipulation of data in a computer. It mainly consists of three parts: arithmetic/logic unit, control unit and register unit. They perform operations, coordinate machine activity, and temporary storage, respectively.

The CPU and main memory

The registers in the CPU are divided into general-purpose registers, which are used to temporarily store data that the CPU is using, and special-purpose registers, which are used for cpu-specific purposes, such as instruction registers and program counters. The CPU communicates with the main memory through the bus, and the CPU can operate the data in the main memory through the control unit.

The process of adding two values is roughly as follows: read the first value from main memory and place it in register 1-> read the second value from main memory and place it in register 2-> Send the value saved in both registers as input to the addition circuit -> save the addition result in register 3-> place the result in main memory in the control unit.

Program equivalent data

Primitive computers did not store programs as modern computers do. In the past, people only stored data, and the steps performed by the device were built into the control unit as part of the computer. This is inflexible, and can only be improved by rewiring. Treating programs and data as essentially the same was a big break, because people had always thought they were different things, that data should be in main memory and programs should be part of the CPU.

It is of great benefit to store programs as data in main memory, from which the control unit can read programs, decode them, and execute them. When we want to modify the execution program we can modify it in the computer’s main memory without having to change or rewire the CPU.

Command system

The program contains a large number of machine instructions, which are decoded and executed by the CPU. Cpus fall into two classes of architecture: Compact instruction set computers (RISC) and complex instruction set computers (CISC). RISC provides the smallest machine instruction set, high computer efficiency, high speed and low manufacturing cost. CISC provides a powerful and rich instruction set that makes it easier to implement complex software.

Machine instructions fall into three categories: data transfer, arithmetic/logic, and control.

Data transfer class instructions are used to move data from one place to another. For example, the LOAD instruction loads the contents of a memory unit into a register, whereas the STORE instruction stores the contents of a register into main memory. In addition, the instructions for the CPU to communicate with other devices (keyboard, mouse, printer, monitor, disk, etc.) are called I/O instructions.

Arithmetic/logic class instructions are used to make a control unit request to perform an operation within an arithmetic/logic unit. These operations include arithmetic, and, or, xOR, and displacement.

Control class instructions are used to direct program execution. Take the JUMP instruction, which includes both unconditional and conditional jumps.

Instruction register and program counter

The CPU loads instructions from main memory to decode and execute, involving two important registers: the instruction register and the program counter. The instruction register is used to store the instruction being executed, while the program counter holds the address of the next instruction to be executed.

The CPU requests main memory to load the instruction at the address specified by the program counter, places it in the instruction register, and increases the value of the program counter by 2 (if the instruction length is 2 bytes) after loading.

How instructions are executed

We want to calculate 11 + 22, for example, assumes that the process is: the contents of main memory address of 00 loaded into the register 1 – > the contents of main memory address of 01 2 – > will be loaded into the register register register 1 and 2 data together and save the results to the register 3 – > will register 3 results stored in the main memory address for the location of the 02 – > to stop.

The CPU is involved in four operations: load, Store, add, and halt. These operations can be coded as 1, 2, 3, 0000, respectively.

1100
1201
3312
2302
0000
Copy the code

The controller

The CPU communicates with other devices through a controller, which can be installed on the mainboard or plugged into the mainboard in the form of a circuit board. The controller itself can be thought of as a minicomputer with its own simple CPU. It used to be necessary to buy a controller for each peripheral, but now with universal serial Bus (USB) becoming the universal standard, many peripherals can directly use USB controller as the communication interface. Each controller is connected to a bus and communicates through the bus.

Each controller may be designed to correspond to a set of address references that are ignored by main memory. When the CPU sends messages to these addresses, it actually goes directly through main memory to the controller, operating on the controller instead of main memory. This pattern is called store mapped input/output. In addition, another implementation of this pattern can provide specific opcodes in machine instructions specifically for communicating with the controller, called I/O instructions.

Direct memory access

Direct memory access (DMA) is a measure to improve the communication performance of peripherals. The CPU does not always need to use the bus, and the controller can take full advantage of the time when the bus is idle. Because the controller is connected to the bus, and the controller has the ability to execute instructions, so some of the CPU work can be assigned to the controller to complete. For example, when retrieving data from disk, the CPU can inform the controller, and the controller can find the data and put it into main memory while the CPU performs other tasks. This saves CPU resources. But DMA can make bus communication more complex and cause bus race problems. The bus bottleneck stems from the Von Neumann architecture.

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