1, LCD MIPI DSI protocol MIPI-DSI is a serial Interface applied to Display technology, compatible with DPI(Display Pixel Interface), DBI(Display bus Interface, Display Bus Interface) and DCS(Display Command Set), send pixel information or instructions to the periphery in a serial way, and read state information or pixel information from the periphery, and enjoy their own independent communication protocol in the transmission process, Including packet format and error correction mechanism.
Mipi-dsi has two working modes: high-speed mode and low-speed mode. All data channels can be used for one-way high-speed transmission, but only the first data channel can be used for low-speed two-way transmission, and the status information and pixel equation of the subordinate end are returned through this data channel. The clock channel is dedicated to transmitting synchronous clock signals during high-speed data transmission. In addition, a host can communicate with more than one slave simultaneously.
A simple diagram of THE LCD MIPI system is as follows:
1.1 miPI DSI protocol layer is mainly divided into four layers: application layer, protocol layer, channel management layer and physical layer
1.2 When the physical layer receives the low-speed transmission request, the logic circuit serializes the instruction or data to be sent and controls the output low-power level with high swing to carry out low-power transmission request. Then the instruction or data is serialized into the channel, and the receiver recognizes the transmission mode to complete the parallel conversion of serial data.
When receives the request, high-speed circuit sends requests for high-speed transmission high swing low consumption level, and then sent the data after serial conversion drive differential drive module with a low swing signal transmitted on the channel, the receiver is to identify the model correctly after testing its sync signal transform high-speed serial data completion string and successfully received.
In addition, the Bus control can be exchanged between the host end and the slave end. The sending end sends the request to abandon the Bus, and the receiving end controls the Bus to initiate the response after receiving the request. The total process is TA(Turn around) operation, which is called BTA (Bus turn-around) in LCD. When the host terminal needs to obtain the status of data received by the slave terminal or read the parameters or display data of the display module, the host terminal initiates TA operation. After the slave terminal sends data, it automatically initiates TA operation and returns the control of the bus.
The signal has two working states, high-speed mode state (LP) and low-speed mode state (HS).
Physical layer, is to control the hardware signal (timing), MIPI-DSI two signal types:
Clock lane, two lines one Dp Dn;
Data lane, two lines one Dp Dn;
There are multiple data lanes as required, including at least one lane (LANe0) and at most four lanes (LANe0, LANE1, LANe2, and LAN3). Only LANe0 is bidirectional (bidirectional in low speed mode and one-way in high speed mode), and all other lanes are one-way (one-way in high speed mode).
Data Lane level:
Low speed mode LP: 0-1.2V, idle level (LP11) Dp,Dn is 1.2V.
High-speed mode HS: 100-300mV (200mV)
According to D – PHY agreement, in the entire agreement of the physical, between the host and slave end USES a synchronous connection, clock channel is used to transmit high speed clock, one or more data channel is used to transmit data signals low power consumption or high speed data signal every channel is the use of two interconnect to connect to the host and slave, High speed and low speed ESCAPE modes are supported.
In high-speed mode, the sender simultaneously drives the only two interconnection lines in the channel to output low-swing differential signals, such as 200mV.
In low-speed mode, the sender drives the interconnect and outputs single-end signals respectively, but the swing is relatively large, such as 1.2V, as shown in the figure below:
Differential transmission module (HS_TX) drives the interconnect with differential signals, and the high-speed channel presents two states: differential-0 and differential-1. The low-power single-ended transmission module (LP_TX) drives the two interconnects independently, and there are four different states on the channel: LP00, LP01, LP10, and LP11. The protocol defines the line level and sets three working modes: high speed mode, control mode and ESCAPE mode. By default, the channel is in control mode and the line is in STOP state. When the channel needs to enter the high-speed mode or ESCAPE mode, the sending module needs to drive the line LP01 or LP10 to send the request to the receiver. After sending the request sequence, the corresponding working mode will be carried out. After sending LP11, the transmission can exit and end and return to the STOP control state. The receiving end needs to carry out LP-RX reception at any time to detect the line level and determine the working mode of the channel.
1.2.1 Clock Channel Clock channel supports high-speed mode and ULPS (ultra-low power mode) mode:
High speed mode applies to the whole interface working in high speed data transmission mode, used to transmit high speed clock:
ULPS mode is used to set the clock channel to ultra-low power consumption when the peripheral (such as the entire display module) enters hibernation mode to save the power consumption of the peripheral interface.
1.2.2 Data Channel Data channel supports high-speed mode and ESCAPE mode, which also includes another important function of bus control exchange — BTA mode. The high speed mode transmits data with high speed and low swing differential signal. The speed is up to 1Gps. After passing through the request sequence LP11->LP01->LP00, HS_TX starts to send serial high-speed data, and at the end of the transmission, LP_TX sends LP11 back to normal control mode.
ESCAPE mode is driven directly by LP_TX line channel to send level sequence to transmit low power data. The entry mode is LP11->LP10->LP00->LP01->LP00, and the exit mode is LP10->LP11. After the request sequence, LP_TX sends mode commands, including trigger command and low power data transmission (LPDT), as shown below:
BTA mode is used to switch bus control, complete in control mode. LP_TX sends the request sequence LP11->LP10->LP00->LP10->LP00 and stops the driver bus after passing through BTA-GO. In contrast to the other end of the bus, after receiving the request sequence and passing through bTA-SURE, LP_TX starts driving the bus, sending acknowledgement signals and taking over the bus.
1.3 The channel management layer is set to have a maximum of 4 data channels according to the design. The data to be sent at the sending end is divided into N groups according to the channel order and sent to the corresponding data channel, so that it can be simultaneously sent to the subordinate end through the data channel. At the receiving end, what the layer needs to do is to combine the N groups of data it receives together to restore the original data sequence.
Data grouping and recovery are shown as follows:
Data grouping:
Data recovery:
Data operation process:
1.4 Protocol layer information transmission adopts packet format, including long packet and short packet. When sending data, packets are compressed according to the information type and content. ECC codes are generated and CRC codes are added. When receiving data, the whole packet is checked and corrected according to the ECC code and CRC code, and the packet header and data content are decoded and properly transmitted to the application layer.
DSI protocol is a communication protocol based on packet transmission. The commands and data transmitted between the host and the display module are basically carried out in packet format. DSI defines two types of data packets: short packet and long packet. The short packet is mainly used for transmitting commands and reading and writing registers, while the long packet is mainly used for transmitting large amounts of image data or partial control commands.
1.5. According to the needs of application modules, the application layer initially encodes the sent commands and data into the format specified by MIPI-DSI at the sending end, and restores the received data to the data format and sequence requirements supported by the application modules at the receiving end.
The application layer module is directly connected to the display module and is responsible for the communication with the display module. In accordance with the agreement requirements, the interface circuit support command mode and video mode, command mode is still host after interface conversion to “command + parameters” format to read and write operations of display module, the video mode, the host can directly display data is written to display module, no need to command operation, real-time display video. The module should support command mode and video mode in the design process.
According to the meaning of data types defined by the protocol, some of these data types are specifically applied to video mode, such as 0x01 which refers to the start of a field synchronization signal (Vsync). Therefore, the circuit design of this module is divided into two modules: video mode application circuit and command mode application circuit. The video mode application circuit module only receives commands and data related to video mode and transmits them to the driver in DPI timing format.
Cmd-mode application circuit module is suitable for non-video mode control commands and data, which are decoded and written to registers or SRAM in DBI sequential format in the display module. When need to read data, the command mode application circuit module through DBI port can read the relevant register information from the display module.
Mipi general block diagram:
2.1 MIPI rate MIPI_CLK = resX * resY * BPS * 1.25 * FPS/lane_num
Note: BPS = 3 * 8 = 24 bits
1.25 for the allowance
Such as:
Resolution: 2560*1440, FPS = 65
MIPI Lane: two data lanes and one clock lane
Mip_clk = 2560144060fps* (38) 1.25 * 65/2/8/104/1024 = 429Mhz
2.2 LCD DSI Schematic Diagram Today, LCD MIPI as an example to do a brief discussion. Display corresponds to MIPI DSI and Camera to MIPI CSI. Related to Display is MIPI DSI, DPI, DBI, etc. It regulates the protocol of communication between host Display controller and panel from physical layer, link layer to application layer.
DPI: Video – mode displays
Class: : DBI: Command – mode displays
2.3.1 A vertical line flashes in the middle of screen switching cause: MIPI CLK_POST is low
Analysis: Data Lane enters LP mode after transmitting the last frame of data, and clKLane continues to transmit clock signal for too short a time, resulting in incomplete entry of datalane into LP11 and unstable state.
Solution:
1. Increase clK_POST
2. Change the clock mode to Continue, resulting in high power consumption
Cause: CLK of MIPI is low, CLK of LK stage is low, and CLK of kernel stage is normal
Analysis: Inconsistent packet length will lead to inconsistent lP11 entry time, which is a normal phenomenon — exclude the problem caused by low LK frequency
Solution: trim frequency
2.4.1. When IOVCC is powered on, MIPI abnormal pulse occurs. At this time, THE MIPI interface is not ready, so LP-TX is opened and abnormal pulse is output
2.4.2, reset low power normally, MIPI signal is pulled down device due to low power consumption consideration, reset is low, into the deep standby mode, regulator closed, protection diode shunt, pull down the signal.
2.5. CLKP, CLKN, DATA0P and DATA0N shall be extracted from MIPI test
Reference:
1, the mipi DSI blog.csdn.net/redredbird/…
Blog.csdn.net/eZiMu/artic…
2, LCD blog.csdn.net/dearsq/arti debugging process…
3. LCD DSI paper
www.doc88.com/p-087738494…