003- Status register

Inside the CPU, there is a special type of register (the number and structure may vary from processor to processor). This kind of register is called status register (CPSR) register in ARM. CPSR is different from other registers, which are used to store data. The whole register has one meaning. The CPSR register works bitwise, meaning that each bit has a special meaning and records specific information.

Note: the CPSR register is 32 bits

  • The lower 8 bits of the CPSR (including I, F, T, and M[4:0]) are called the control bits and cannot be modified by a program unless the CPU is running in privileged mode!
  • N, Z, C, and V are all conditional code flag bits. Their contents can be changed by the results of arithmetic or logical operations, and can determine whether an instruction is executed or not! Significant!

N indicates Negative

Bit 31 of the CPSR is N, the symbol flag bit. It records whether the result is negative after the relevant instruction is executed. If it’s negative N is equal to 1, if it’s non-negative N is equal to 0.

Note that in the ARM64 instruction set, some instructions that affect the status register, such as add, sub, or etc., are mostly operational instructions (perform logical or arithmetic operations).

Z (Zero)

The 30th bit of CPSR is the Z, 0 flag bit. It records whether the result is 0 after the relevant instruction is executed. If the result is 0, then Z = 1. If it’s not 0, then Z is equal to 0.

For the value of Z, we can see in this way,Z marks whether the calculation result of relevant instructions is 0. If it is 0, N should record such positive information as “yes”. In computers, 1 means logical truth, positive. So when the result is 0 Z = 1 means “the result is 0″. If the result is not 0, Z records the negative message” not 0″. In computers, 0 means logic false, means negation, so when the result is not 0, Z = 0 means “the result is not 0”.

C (Carry)

Bit 29 of the CPSR is C, the carry flag bit. In general, unsigned numbers are performed. Addition operation: C=1 if the operation results in a carry (unsigned overflow), otherwise C=0. Subtraction operations (including CMP) : C=0 when a debit occurs (unsigned overflow), otherwise C=1.

For an unsigned number with bits N, the highest bit of the corresponding binary information, i.e., the n-1st bit, is its most significant bit, while the imaginary NTH bit is the higher bit relative to the most significant bit. As shown below:

carry

We know that when two pieces of data are added, it is possible to produce a carry from the most significant bit to a higher one. For example, two 32-bit bits of data: 0xAAAAaAAA + 0xAAAAaAAA will produce a carry. Since the carry value cannot be stored in 32 bits, we simply say that the carry value is lost. In fact, the CPU does not discard the carry system, but records it in a special register. ARM uses C bits to record the carry value. For example, the following command

mov w0,# 0 xaaaaaaaa; The binary of 0xA is 1010Adds w0, w0, w0; After execution equals 1010 << 1 carry 1 (unsigned overflow) so C is marked with 1 adds W0,w0,w0; After execution equals 0101 << 1 carry 0 (unsigned without overflow) so C is marked with 0 adds W0,w0,w0; Repeat the above to add W0,w0,w0Copy the code

A borrow

When you subtract two numbers, it’s possible to borrow higher. For another example, two 32-bit data: 0x00000000-0x000000FF will generate a debit. After the debit, it is equivalent to calculating 0x100000000-0x000000FF. I get the value 0xffffFF01. Since we borrowed one bit, the C bit is used to mark the borrowing. C = 0. For example:

mov w0,#0x0
subs w0,w0,#0xff ;
subs w0,w0,#0xff
subs w0,w0,#0xff
Copy the code

V(Overflow) Indicates the Overflow flag

Bit 28 of the CPSR is V, the overflow flag bit. When a signed number operation is performed, if it exceeds the range that the machine can identify, it is called an overflow.

  • Positive + positive overflow for negative numbers
  • Negative + negative is positive overflow
  • Positive and negative numbers cannot overflow