Writing in the front
Today, we continue to update the Advanced Programmer series, which takes you from zero to programmer. Next, let’s talk about the structure and taxonomy of computers.
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Computer architecture
Computer structure is mainly composed of arithmetic unit, controller, memory, input device and output device. The simplified structure is shown in the figure below.
Next, let’s take a look at its detailed structure as shown below.
The main memory is also called internal memory, that is, memory; Auxiliary storage is also called secondary storage, which is external storage, such as a disk; The core components of CPU are arithmetic unit and controller.
The CPU consists of an arithmetic unit, a controller, a register bank and an internal bus.
Arithmetic unit includes: arithmetic logic unit, accumulative register, data buffer register, state condition register.
- Arithmetic logic unit (ALU) : Arithmetic and logical operations of data.
- Accumulator register (AC) : General purpose register that provides a workspace for the ALU for temporary data storage.
- Data buffer register (DR) : Temporary storage of instructions or data while writing to memory.
- State Condition Register (PSW) : Stores state and control flags, and sometimes the state condition register can also be classified as a controller part.
The controller includes: program counter, instruction register, instruction decoder, timing unit.
- Program counter (PC) : The address where the next instruction to be executed is stored.
- Instruction register (IR) : Stores instructions to be executed.
- Instruction decoder (ID) : Analyzes and interprets the opcode fields in instructions.
- Timing component: Provides timing control signals.
Computer architecture classification
First of all, let’s take a look at a classical method to classify the computer architecture in the field of computer, namely Flynn classification, which divides the computer into single instruction flow single data flow, single instruction flow multi-data flow, multi-instruction flow single data flow and multi-instruction flow multi-data flow.
For details, see the following table.
| Architecture type | structure | The key features | On behalf of |
|---|---|---|---|
| Single instruction stream Single data stream (SISD) | Control: one processor: one main memory module: one | Uniprocessor system | |
| Single instruction stream Multiple Data Stream (SIMD) | Control: One processor: Multiple main memory modules: multiple | The processors perform the same alert asynchronously | Parallel processor, array processor, super vector processor |
| Multiple instruction stream Single data stream (MISD) | Control: Multiple processors: one main memory module: multiple | Proved impossible, or at least impractical | At present, there is no data to record pipelined processor as such |
| Multiple Instruction Stream Multiple data Stream (MIMD) | Control: Multiple processors: Multiple main memory modules: multiple | Can realize operation, task, instruction and other levels of comprehensive parallel | Multiprocessor system, multicomputer |
Basic concepts of instruction
An instruction is a statement in machine language, a meaningful set of binaries, and the format of the instruction is shown below.
Among them, the opcode part indicates the nature of the operation to be performed by the computer, such as addition, subtraction, fetch, store, etc. Address code field needs to contain the address of each operand and the storage address of operation result, etc. From the perspective of address structure, it can be divided into three address instruction, two address instruction, one address instruction and zero address instruction.
Three address instruction
For example, the three-address instruction is used when performing a+b=c operation. This is as follows.
Two address instruction
For example, when executing a+=b, the two-address instruction is executed, as shown below.
One address instruction
For example, executing a++ is an address instruction, as shown below.
Zero address instruction
For example, an outage is a zero address instruction.
Addressing mode
Generally speaking, addressing can be divided into: immediate addressing, direct addressing, indirect addressing, register addressing, register indirect addressing.
- Immediate addressing: The operands are directly in the instruction, which is fast and less flexible.
- Indirection: The address of the operand stored in the instruction.
- Indirection: An instruction stores an address that corresponds to the address of the operand.
- Register addressing: Registers hold operands.
- The registers hold the addresses of the operands.
CISC and RISC
CISC and RISC represent complex instruction set system and compact instruction set system respectively. The following table describes the specific information.
| Instruction system type | instruction | Stub way | implementation | other |
|---|---|---|---|---|
| CISC (Complex) | Large quantity, use frequency difference, variable length format | Support for multiple | Microprogram control technology (microcode) | Long development cycle |
| SISC (Streamlined) | Small number, close frequency of use, fixed-length format, mostly single-cycle instructions, operating registers, only Load/Store operating memory. | Lack of support | Increased communication register, hardwiring logic control, suitable for pipelining | Optimized compilation, effective support for high-level programming languages |
How to compare CISC and RISC, in what dimensions?
Instruction number, instruction frequency, memory mode, registers, pipeline support, high-level language support.
- CISC: complex, large number of instructions, large frequency differences, multiple addressing.
- RISC: Compact, with fewer instructions. Operating registers, Single period, less addressing, Multiple universal registers, pipeline,
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