FPGA/ASIC written test interview questions Highlights (1) Knowledge points high-frequency repetition exercises

Writing in the front

In fact, this article is the integration of the last autumn recruitment summed up the pen test questions or exercises of the major platforms, but last year as a result of the side of the written interview summary, more rough, here again to retouch, predecessors planted trees, convenient for descendants to enjoy the shade! Note: Personal wechat official account, Jianshu, Zhihu are also constantly releasing articles oh!

• Personal wechat public account: FPGA LAB;

• Jane address: Reborn_Lee’s Jane home page

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This article is from:

• FPGA Pen analysis (1)
• FPGA Pen analysis (2)
• FPGA Pen analysis (3)
• FPGA Pen test analysis (4)

Note: Since external links cannot be added to the wechat official account, you can choose to read the original text or directly enter my CSDN blog to read, in order to get a better reading experience!

Body content

Describe the ASIC design process and the tools used in each part.

To be honest, I have never done ASIC before, but I often encounter the topic of comparing ASIC and FPGA development, so I have to take the initiative to understand the ASIC design process:

Baidu’s interpretation of ASIC (understanding) :

ASIC: Application Specific Integrated Circuit, is a kind of Integrated Circuit designed for a Specific purpose.

Modern ASIcs often contain the entire 32-bit processor, memory units like ROM, RAM, EEPROM, Flash, and other modules. Such asIcs are often called soCs (System on chip).

FPGA is a close relative of ASIC. In general, the digital system is modeled by schematic diagram and VHDL, and the network table based on some standard libraries is generated by EDA software simulation and synthesis, which can be used when configured to the chip. The difference between it and ASIC is that users do not need to intervene in the layout and wiring of the chip and process problems, and can change its logic function at any time, the use of flexible.

ASIC design process

The process given in this article is for reference:

Detail the ASIC design process

Flow chart:That is:

• Requirements (Requirements)
• Technical Specifications
• Architecture (Architecture)
• Digital Design
• Validation (Verification)
• Logic Synthesis
• Logical Equivalence
• Placement and Routing
• Verification (Validation)

Specific meaning, please go to address: detailed explanation of ASIC design process view!

You can also refer to the following flow chart:

There are:

The general process is similar, you can say about yourself, there is no need to cover everything!

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Describe the development process of FPGA?

The FPGA development process can be seen from THE FPGA development tool ISE or Vivado, such as ISE:

As Vivado:

The summarized process is as follows:

For a more detailed process, see this:

The corresponding document of this figure is: download from here, if there is no, it means to be harmonious, you can contact me or download the paper by yourself

The following processes can be seen from ISE and Vivado development tools:

• RTL code preparation, can use schematic, Verilog HDL and VHDL to develop,
• Then we can do functional simulation to verify whether the design is correct and logical,
• You can then synthesize and map RTL code to basic logic gate units, triggers.
• Then implement, including three steps:

1. Translation, mapping and layout.

XIlinx FPGA Development Basic Process (I) (General introduction)

This is in ISE some routines, in Vivado development tools can not be so complex, Vivado generated network table formula is consistent, not ISE so many, so miscellaneous. Finally generate bit stream file, burn (programming) into FPGA.

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Noun explanation

3. ROM: Read Only Memory, the Memory of a mobile phone, computer, etc.

RAM: Random Access Memory.

SRAM: Static random-access Memory, also known as Volatile Memory. SRAM: Static random-access Memory, also known as Volatile Memory. SRAM: Static random-access Memory, also known as Volatile Memory

DRAM: Dynamic Random Access Memory, the main principle is to use the capacitor storage charge to represent the number of a bit is 0 or 1, due to the leakage current phenomenon of the transistor, the capacitor will discharge, so to periodically charge the capacitor, called refresh. Srams retain data loss without flushing, but both lose data after a power outage, known as Volatile Memory

SDRAM: Synchronous Dynamic Random Access Memory, Synchronous DRAM for writing and reading data.

Electrically Erasable Programmable Read Only Memory. Electrically Erasable Programmable Read Only Memory.

DDR: Double Data Synchronous Dynamic Random Access Memory, SDRAM with Double rate transmission, Data can be transmitted on both the rising and falling edges of the clock. The memory chips in our computers are DDR chips.

FLASH: FLASH Memory, non-volatile solid state storage, such as Memory cards or USB FLASH drives.

I’ve summarized this before:

• RAM bsde

• ROM bsde

• IP core soft core, hard core, solid core brief notes

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System transformation

• Convert R to decimal: expand by weight and add

• Conversion of a decimal number to an R-base number: Part of an integer, mod by R, divided until the quotient is 0. So, the decimal part, you multiply it by R, you multiply it by 0.

• Binary numbers to octal numbers: a group of three digits, the integer part of the left side of the complement 0, decimal part of the right side of the complement 0. And vice versa.

• Hexadecimal number: a group of four digits in which 0 is added to the left of the integer part and 0 is added to the right of the decimal part. And vice versa.

What is competition and adventure? How to eliminate?

I’ve written a series of articles like this before, from the Way of FPGA:

competition

If at a certain moment, there are more than two electrical signal paths from an input end of the combinatorial logic to its output end, it is said that the combinatorial logic is competing against the input end in the current state.

For example:

When B=1 and C=1, the circuit can be simplified as:

The input is A prior to not (A) A non-arrival or gate. Therefore, if A is initially set to 1, not (A) is 0. After A changes to 0, A short zero pulse appears in the output because A arrives first at or gate, which is not expected.

It is called competition when the signal reaches a confluence point in different transmission paths, and it is called risk when the circuit output makes an instantaneous error. The simplest way to avoid it in FPGA design is to use timing logic to synchronize input and output as far as possible.

The method of eliminating danger in FPGA:

The most representative backward elimination method is time series sampling method, which is the most widely used in all kinds of methods. It can be said that as long as you are describing a sequential logic, you have used sequential sampling, either intentionally or unintentionally, to eliminate danger.

Sequential sampling is almost universal because there is always a maximum delay path between the input and output of any combinatorial logic. Let the maximum path delay be T. If its input remains unchanged after changing once at time 0, its output will definitely be stable to the corresponding output of the new input after time T, and between time 0 and time T, the output of the combined logic may appear a series of unstable phenomena.

Therefore, if the combinational logic is part of the synchronization logic, we only need to appropriately select the signal with a period greater than T as the clock to bypass the problematic time from 0 to T and sample the stable and correct output after time T. In addition, since the input of the combination logic will remain unchanged for at least time above T after each change, the output can also be guaranteed to have enough time to reach stability. Thus, the greatest advantage of the sequential sampling method is that it does not care about the contents of combinatorial logic at all, so it is widely applicable.

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2 frequency division description

D flip-flop with synchronous high set and asynchronous high complex end of the binary frequency circuit, draw the logic circuit, Verilog description!

module freq_div2(
input clk,
input rst,
input set,
output reg Q
); always@ (posedge clk or posedge rst)begin if(rst == 1'b1)  Q <= 1'b0; else if(set == 1'b1)  Q <= 1'b1; else  Q <= ~Q; end  endmodule Copy the code

Generate RTL circuit diagram with Quartus:

I tried to use ISE generation, but the only thing I am not satisfied with with ISE is the generation of this graph, which looks dazzling and not simple:

Of course, the resulting schematic is exactly the same, just a matter of component style. Quartus is closer to handwriting.

For comparison’s sake, the Vivado schematic is also concise:

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Describe the establishment time and hold time.

Setup time Tsu (setup) : The minimum time that the data input of a trigger must remain unchanged until the rising edge of the clock arrives.

Hold time Th (hold) : The minimum time that the data input of a trigger must remain unchanged after the rising edge of the clock arrives.

That’s still too simple a question to ask, but it could still be used in an interview!

I have summarized the establishment time and hold time related pen questions for your reference, please skip to the following link:

Create time and hold time test type summaries

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What is the difference between a trigger and a latch?

The latch is sensitive to the level signal and changes its state under the level action of the input pulse.

D trigger is sensitive to the edge of the clock and detects that the rising edge or falling edge triggers an instant change in state. The following link is a collection of Internet references to the differences between triggers and latches:

Triggers and latches

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Compute the minimum period?

Tco: register update delay, clock output delay, the maximum delay time when the clock triggers the data output

Minimum clock period: Tmin = Tco + Tdata + TSU-tskew. Maximum frequency Fmax = 1/Tmin

Tskew = Tclkd – Tclks.

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What are Clock Jitter and Clock Skew, and what is the difference between them?

Clock Jitter: Clock Jitter is a characteristic of the Clock source and Clock signal environment. It can be defined as “the deviation of the edge of the clock from the ideal position”. Clock jitter is usually caused by clock generator circuits, noise, power changes, interference from nearby circuits, etc. Jitter is an influence on the design margin specified for timing convergence.

The diagram below:

The blue clock represents the ideal clock, and the red line represents the problems that can occur with jitter clock edges.

Clock jitter can cause many problems, such as:

Here, for further reading, is a document on clock jitter:

Clock Jitter Definitions and Measurement Methods

If not, on behalf of harmony, you can contact me (public number: FPGA LAB or CSDN: Li Ruibo)

Clock Skew: Also known as Clock Skew, is caused by different wiring lengths and loads, resulting in inconsistent time for the same Clock signal to reach two adjacent timing units.

The diagram below:

Choose to see

As an example of circuit failure operations due to clock skew, consider the first two steps of the serial input shift register shown above. Both edge-triggered DFF’s are fed from the same clock source, but Ck + t D’s clock input to FF2 is td delayed relative to Ck’s clock input to FF1. Input data from data to FF1 is transmitted to its output Q 1 at the time t F after the rising edge of Ck. Q 1 is also the data input to FF2. If T d> tf, the input data is transmitted to the output of FF2 at tf after Ck + t d rising edge. When a single clock pulse is received, the input data has been transferred through the two stages of the shift register. Since there is no combinatorial logic between each level of the shift register, it is obvious that the clock offset problem is particularly important in the design and operation of the shift register. If TD < tf, I’m afraid the second level flip-flop will sample the data incorrectly.

Difference: Jitter is generated in the clock generator, and related to crystal oscillator or PLL internal circuit, wiring does not affect it. Skew is caused by different routing lengths resulting in different delay of the arrival of the rising edge of the clock in different paths.

For more, go to the links below and to more resources at the end of this article:

Difference between clock jitter and clock skew

What is metastable state, what causes it, and how can it be eliminated?

This is covered in detail in the blog post on metastability

Too much space, give a brief explanation:

If the input voltage sampling time of the flip-flop is too short, that is, the timing is insufficient, it will take a long time for the flip-flop to achieve the output logic to reach the standard level. That is, the circuit will stay in the intermediate state longer, making the circuit slow to “react”, which is called “metastable”. (For example, the input signal changes between the establishment time and the hold time of the effective edge of the clock, leading to the failure to meet the establishment time or hold time of the trigger, resulting in a period of unstable output state, that is, metastable.)

Elimination: synchronization of two or more registers. In theory, metastable state can not be completely eliminated, but can only be reduced. Generally, the occurrence probability of metastable state can be greatly reduced by using two-stage trigger synchronization, and the improvement of the occurrence probability of metastable state can not be improved by adding multi-stage trigger.

Note, however, that double flip-flops as synchronizers can only be used for single-bit data transmission. Asynchronous FiFO is generally used for multi-bit data operations.

Asynchronous FIFO see link:

FPGA basic knowledge minimal tutorial (4) from the FIFO design of asynchronous FIFO

Reference code:

reg data_mid;

reg data_out;

always@ (posedge clk or negedge rst_n)begin
  if(! rst_n)begin   data_mid <= 1'b0;   data_out <= 1'b0;   end   else begin   data_mid <= data_in;   data_out <= data_mid;   end  end Copy the code

Synchronous versus asynchronous?

What is the difference between synchronous and asynchronous reset?

Synchronous reset is to determine whether it is effective when the edge of the clock is triggered, and the clock. Asynchronous reset is the reset signal valid and clock independent.

Such as asynchronous reset:

Synchronous reset:

For a more detailed introduction to the reset strategy, see the link below:

Reset Design Strategy

Or:

If the reset policy cannot be downloaded, it represents being harmonized. You can contact my personal wechat public account FPGA LAB or CSDN: Li Ruibo to obtain it.

The difference between synchronous and asynchronous logic

Synchronization logic is that clocks have a fixed causal relationship. Asynchronous logic is that there is no fixed causal relationship between clocks

Synchronous and asynchronous circuits are different

The synchronous circuit has a unified clock source. The module driven by the clock after PLL frequency division is still a synchronous circuit because it is a unified clock source driver. Asynchronous circuits do not have a unified clock source.

Talk about understanding Retiming technology

Retiming is to readjust the timing sequence. For example, when complex combination logic is encountered in the circuit and the delay is too large, the timing sequence of the circuit is not satisfied. In this case, pipelining technology is adopted.

For example, you can change the register position to reduce the minimum clock period:

Retiming retiming retiming retiming

Note: if you can’t open it, forget it!

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What is a high resistance state?

High impedance state:

An output state of a circuit that is neither high nor low and has no effect on the lower circuits if the high resistance state is entered into the next circuit. It can be understood as a circuit break and is not driven by anything or anything.

I have previously written a blog about high resistance states: [FPGA] Bus implementation form of three state gate

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Integrated Clock Gating Cell

I’ve also written about gated Clocks before: Gated Clocks

Clock gating is a common technique to reduce clock power consumption by turning off the module clock with the clock enabling signal. Clock gating only requires an AND OR OR gate. Consider that you are using an AND gate with a clock. The high EN edge may appear at any time and may be inconsistent with the clock edge. In this case, the output of the AND gate will be 1 less than the clock duty cycle. You end up with burrs in the clock signal.

To avoid this, a special clock gating unit is used, which synchronizes EN with the clock edge. These are called integrated clock gating units or ICGs.

There are generally two types of implementations:

The following link provides the following methods: Integrated Clock Gating Cell

And gate implementation:

Or gate implementation:

Using a gated clock can reduce power consumption because the clock is only provided in the En valid range.

More resources

• BestFPGADevelopmentPractices
• ASIC Design Flow
• clock jitter
• clock_uncertainty
• clock skew
• Controlling Clock Skew
• difference-between-synchronous-and-asynchronous-sequential-circuits
• synchronous_and_asynchronous_cir
• retiming
• Integrated Clock Gating Cell

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