Hello everyone, I am a ruffian balance, is a serious technical ruffian. ARM Cortex-M stack mechanism

Today to share this article is still before 2016 ruffian Heng wrote technical documents, took some time to rearrange the format. Ruffian balance in front of the “embedded stack principle”, this is the stack principle of engineering practice, more specifically in the ARM Cortex-M application. The ARM Cortex-M family has been developed for many generations, and we will use the simplest cortex-M0 as an example to describe the stack mechanism:

1. Ground rules

1.1 R13 / SP register

R0-r12 are general purpose registers, and R13 is system stack pointer SP, which is used to access the stack, that is, the RAM area of the system. The cortex-M0 uses two stack Pointers: the main stack pointer (MSP) and the process stack pointer (PSP). R13 can only be one or the other at any time. The default is MSP and can be changed via the control register (CONTORL).

The MSP is the specified SP (the first 4 bytes of the vector table are automatically loaded) after the system is reset (i.e., it is in Handler Mode). It is used to handle exceptions. When Reset_Handler is finished, the CPU is in Thread Mode, and only the PSP and MSP can be used in this state. If a hard interrupt occurs, the Handler Mode is displayed. If the hardware interrupt is complete, the Thread Mode is returned.

For MSP and PSP, it is configured through the CONTORL register. The CONTORL register can only be set in Thread Mode. In general, there is no need to use the PSP, unless there is an OS and the MSP is used as the SP for the OS kernel and the PSP is used as the SP for the Thread level app. The two SPS should be strictly separated. In the compiler, the stack can be accessed via R13 (R13) or SP (SP) (MSP and PSP depending on the environment at the time); The MSP and PSP can also be accessed through the specified MRS and MSR instructions.

1.2 the stack structure

No OS stack structure:

Have OS stack structure:

1.3 stack operation

The stack direction in Cortex-M0 is a full stack mechanism that grows to the lower address. Stack operations are performed through pushes and pops.

The stack is usually placed in the high level RAM area of the ARM, for example, the RAM address of an MCU is 0x20000000-0x20007FFF (32 kbytes). With a stack size of 4 kbytes, the address is usually placed in 0x20007000-0x20007FFf, where 0x20007000 is the absolute top of the stack and 0x20007FFc is the absolute bottom, and SP always points to the relative top. The first PUSH data is stored at the absolute bottom of the stack (which is also the relative top). In fact, except for the POP instruction that can fetch data from the top of the stack; The MOV instruction can also fetch data from any location without affecting the stack structure (i.e., its SP). Since all the ARM registers are 32bit, PUSH and POP instructions are 32bit access, so the SP pointer is always at least 4Byte aligned (the lower 2bit is always 0). Sometimes the compiler will also assign an 8Byte aligned stack. This is because the double floating-point type takes up 8bytes, so the stack is 8Byte aligned for convenience.

2. Stack sequence

The stack order varies with the compiler, processor system, and OS. C does not enforce the stack order. Here we mainly describe the ARM Cortex-M series processor in the case of the specified compiler stack order.

2.1 General Function Calls (General)

The figure above shows what happens to sp when a general function (no parameters, no local variables, no return value) is nested. When executing BL FunctionA instructions, LR records the next sequential instruction of BL FunctionA. The first operation performed after entering FunctionA is PUSH {LR} to PUSH the next sequential instruction onto the stack before executing the FunctionA body. After executing the function body, POP the top data into PC with the POP {PC} instruction to return to the next sequential instruction to continue executing BL FunctionA.

2.2 Extreme function calls (platform by platform)

Consider an extreme case to elaborate on the pushing order, where a function has more than four arguments, multiple local variables are defined in the function body, and there are return values. This situation is special, riffraff balance has done an experiment on IAR, see the following figure:

ARM Cortex-M stack mechanism

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