Nowadays, with the rapid development of digital chip technology, digital semiconductor chip has penetrated into every field of social life, from consumer electronic products, industrial automation equipment to aerospace technology can be seen semiconductor chip technology figure. The country’s investment and attention to chip technology has also been promoted to the strategic level, chip design and manufacturing is becoming a new generation of national importance.

What is EDA?

EDA is the mother of chips, is the pearl on the crown of the chip industry, is the most upstream integrated circuit design, the highest end of the industry. EDA (Electronic Design Automation) is the abbreviation of Electronic Design Automation, THE development of EDA has experienced CAD, CAE and other stages, with the development of integrated circuit technology, EDA is more and more industry to “chip Design software tools”. In 2018, the global output value of integrated circuits was nearly 500 billion US dollars, and the import value of China’s integrated circuits was over 300 billion US dollars. EDA is the source of the capacity performance of the integrated circuit industry, from simulation, synthesis to layout, from front end to back end, from analog to digital and then to mixed design, as well as the process manufacturing behind. EDA software tools cover all aspects of IC design, wiring, verification and simulation, is the “cradle” of the IC industry.

Using EDA tools, engineers will chip circuit design, performance analysis, design IC layout of the entire process by the computer automatic processing completed. Before the advent of EDA tools, circuit design depended on hand, but for large-scale integrated circuits with hundreds of millions of transistors design by hand is simply impossible. It can be said that with EDA tools, there is the possibility of vlSI design.

Hdl-hardware Description Language (HDL-HARDWARE Description Language) is a high-level computer Language used for designing Hardware electronic systems. It describes the logical functions, circuit structures and connection forms of complex electronic systems in the way of software programming. Hardware description language is an important part of EDA technology and a very important software tool in EDA design and development.

At present, major suppliers of EDA software at home and abroad include Synopsys, Cadencen, Mentor Graphics, Huada nine Days, Core Vision, Xinhe Technology, etc. EDA applications cover the design and manufacture of general and special chips and other scenarios.

02 EDA workflow and IO features

A typical EDA workflow includes the following stages:

— Front-end design stage (logical design)

  • The design specification
  • Functional verification
  • synthetic
  • Logic validation

— Back-end design stage (physical design)

  • Layout and wiring
  • Static time series analysis
  • Physical verification

— Production and manufacturing

  • Flow sheet

These phases interact to form EDA’s digital design flow:

In the front-end design stage, engineers complete chip design by compiling source files such as VHDL into chip models, and then verify chip design by distributing tasks in large computing clusters. The scheduler distributes simulation and emulation tasks to different compute nodes that access the back-end chip model by sharing a file system. In the whole front-end design process, engineers need to constantly improve the design, the whole process requires many iterations, so the front-end design stage will generate a lot of simulation work. The efficiency with which build and simulation jobs are created, scheduled, and executed determines how long it takes to bring a chip to market.

EDA applications need to read and compile millions of small source files to build and simulate chip designs when a large number of jobs run in parallel, resulting in a large IO load. The back-end shared file store manages various chip design directories and files so that different users, scripts, and applications can access the data.

In the front-end validation phase, data access patterns tend to be random with lots of small files. The front-end workload requires extremely high concurrency to accommodate the parallel access of a large number of jobs that generate a large number of randomly accessed IO. In addition, because of the large number of small file accesses, this phase can be extremely challenging for metadata access performance.

From some public data, in the semiconductor chip design process, calls to metadata (including GETATTR, ACCESS and LOOKUP) account for more than 85% of all calls, and “read” and “write” less than 15%. The distributed file storage architecture of traditional NAS arrays or single MDS will face great challenges.

In the back-end design and validation phase, the data access pattern will be predominantly sequential. Back-end design phase workloads tend to consist of a small number of tasks that have sequential IO access characteristics and run for a long time. The tasks in the back-end design stage mainly test the parallel access bandwidth of the back-end file system.

Considering the IO access characteristics of front-end design and back-end design, EDA chip design and simulation have high requirements on metadata and data, IOPS of small files and sequential access bandwidth of large files. This process is similar to the IO characteristics produced during parallel compilation of large programs, such as the Linux kernel.

The output of all the jobs involved in the chip design phase may produce terabytes of data. Although some of the data is temporary (such as timing simulations), it still requires the highest level of storage performance to secure the entire chip design process.

According to a report released by semiconductor industry giant Intel, computing and storage CAGR has reached more than 30% of Intel’s internal infrastructure investment for semiconductor design and manufacturing over the past 10 years without reducing any IDC sites.

While Intel may lead the EDA scenario, we can see from industry data that the vast majority of semiconductor design companies are increasing their infrastructure spending by more than 20% a year.

03 How to Meet the Storage requirements in EDA Scenarios

File storage master

In the storage system, EDA workflow is to share and access a large amount of data through the file system, and generate deep directory structure in the system, making the file system in EDA storage system dominant.

YRCloudFile high-performance distributed file storage, with excellent performance, flexible horizontal scalability, and massive small file storage capabilities, can meet the requirements of large-scale computing clusters in EDA applications to access data in parallel in file mode.

Ultra high concurrency performance

Most EDA workflows require extremely high concurrency, and YRCloudFile can meet the concurrency requirements of thousands of high-performance Linux computing clusters, providing far higher concurrency than standard NAS protocols (NFS, SMB).

The large number of metadata operations generated in EDA workloads can be met and matched by the flexible extensible metadata service YRCloudFile, which addresses the metadata performance requirements of EDA workloads.

Flexible and elastic expansion

During the execution of EDA workloads, TB-level data or intermediate results are generated. YRCloudFile distributed file system uses a distributed architecture to centrally manage all disks and provide a unified namespace. It supports horizontal expansion of capacity and performance and can achieve rapid expansion on demand to meet the requirements of EDA for large-capacity storage.