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preface
Introduction of computer composition principle, mainly from the second edition of “computer composition principle” edited by Tang Shuofei.
How are high-level languages executed by computers?
The first computers did not have microinstruction systems. Since BOTH M0 and M1 exist in practice, they are divided into microprogram machines and traditional machines to distinguish them.
Programs that translate high-level languages into machine languages are called translators, and translators are divided into two types: compilers and interpreters:
- Compiler: translate all high-level languages into machine languages at once
- Interpreter: translate a sentence to execute a sentence, re-execute need to translate again
Computer architecture
Computer architecture is an abstract description of the composition of a computer, indicating what parts the computer should contain, such as instruction sets, data types, memory addressing techniques, I/O mechanisms, etc. Implementations vary from vendor to vendor, but for developers of high-level languages, they are transparent, meaning that low-level implementation differences do not affect upper-level applications.
The basic components of a computer
Characteristics of von Neumann’s computer
- A computer consists of an arithmetic unit, a memory unit, a controller, an input device and an output device
- An instruction consists of an opcode (indicating the nature of the operation) and an address code (indicating the location of the operand in memory)
- Instructions and data are represented in binary
- Instructions and data are stored in memory on an equal footing and are accessible by address
- Instructions are stored sequentially in memory and are usually executed sequentially. However, the order of execution can also be changed according to the results of operation or the conditions set
- The machine takes the calculator as the center, the data transmission between the input and output devices and the memory is completed by the calculator
Computer hardware block diagram
A modern computer can be thought of as consisting of three Main parts: CPU, I/O device, and Main Memory (MM), as shown in the following figure:
- M⋅M (Main Memory) : Main Memory, often referred to as Memory, exchanges information directly with the CPU. In addition, there are auxiliary storage, such as hard disk, U disk, etc.;
- 17. ALU (Arithmetic Logic Unit)
- CU (Contro Unit) : Control Unit that interprets instructions in memory and issues various commands to execute instructions.
Detailed block diagram of computer composition
In order to visualize the working process of the computer, the block diagram of the composition of the modern computer is refined:
Arithmetic unit
An algorithm contains at least three registers (modern computer processors tend to have general-purpose registers inside, such as the ARM Cortex-A8 processor, with 40 32-bit registers (32 general-purpose registers, 7 state registers, 1 program counter (PC, Program Counter)) and an arithmetic logic operation unit (ALU).
- ACC (Accumulator) : an Accumulator
- MQ (Multiple-Quotient Register) : Multiple Quotient register
- X: operand register
The controller
The controller is the nerve center of the computer, and it directs all parts to operate automatically and harmoniously. Specifically:
- Read instruction: Command storage reads an instruction
- Parse instruction: Indicate what operation the instruction needs to do and indicate the address of the operand by addressing characteristics
- Execute instruction: Perform an operation based on the address of the operand and the opcode of the instruction
The controller consists of Program Counter (PC), Instruction Register (IR) and control unit (CU) :
- PC: store the Address of the current instruction to be executed, and the main storage MAR (Memory Address Register, Memory Address Register) has a direct access, and has the function of automatic +1, can automatically form the Address of the next instruction
- IR: stores the current instruction and its contents to the self-stored MDR. The OP code (OP(IR) in IR is sent to the CU to analyze the instructions. Its address code (Ad(IR)) is sent to MAR as the address of the operand
- CU: Analyzes the operations required by the current instruction and issues sequences of microoperations to control all controlled objects
Main memory
Main memory (referred to as main memory or memory) includes storage M, various logic components and control circuits, etc. The storage body consists of many storage units, and each storage unit contains many storage elements, each of which can store a binary code 0 or 1. Visible a storage unit can store a string of binary code, called the string of binary code as a memory word, the number of bits of this string of binary code is called the memory word length. The storage word length can be 8 bits, 16 bits, 32 bits, etc. A storage word may represent a binary number, a string of hexadecimal characters, two ASCII codes, or an instruction.
Each storage unit has its own address. The working mode of main storage is to read and write the storage words according to the address of the storage unit, while MAR and MDR are used to achieve access by address:
- MAR: Memory Address Register (MAR) : stores the Address of the storage unit to be accessed. The number of bits corresponds to the number of storage units. For example, MAR is 32 bits, 2^32 = 4 x 1024 x 1024 x 1024 (1024 is denoted as 1K) storage units
- Memory Data Register (MDR) : a Memory Data Register that stores the Data (codes or instructions) read from or written to the storage. The number of bits and the length of the stored word
Of course, in order to achieve a complete read/write operation, the CPU also needs to send various control signals to main memory, such as read commands, write commands, address decoding drive signals, etc.. With the development of hardware circuits, main memory is made into lsi chips, and MAR and MDR are integrated into CPU chips.
The storage word length of the early computer is generally the same as the instruction word length and data word length of the machine, so a visit to the main memory can take one instruction or one data. With the continuous expansion of computer applications, the instruction word length and data word length are often required to be variable. In order to accommodate the variability of instruction word length and data word length, the length is no longer determined by the storage word length, but is represented by the number of bytes. For example, a 4-byte instruction word is 32 bits, and a 2-byte instruction word is 16 bits. At this point, the instruction word length, data word length, and storage word length need not be equal, but must all be multiples of bytes.
The following figure shows the organization structure of ARM memory in 32-bit architecture, and its basic data types are:
- Byte: 8 bits.
- HalfWord: half-word, 16 bits (half-word must be aligned with 2-byte boundaries);
- Word: Word, 32-bit (Word must be aligned with a 4-byte boundary);
- Double World (Cortex-A support) : Double word, 64-bit (Double word must be aligned with 8-byte boundaries).
The main technical specifications of computer hardware
Machine word length
Machine word length refers to the number of bits of binary data that a computer can process in a single integer operation (an integer operation is a fixed-point integer operation). Because the number in the computer is represented by fixed point number and floating point number points, fixed point number and fixed point integer and decimal points, the integer operation said here is fixed point integer operation. The machine word length is also the word length of fixed point number operation of arithmetic unit, that is, the number of bits of general register.
The main memory word length is generally equal to the machine word length, and in different cases, the main memory word length is generally less than the machine word length. For example, the machine word length is 32 bits, and the main memory word length can be 32 bits or 16 bits.
The Windows 64-bit operating system is designed for the CPU with 64-bit machine word length. At present, the 64-bit architecture implementation technology mainly includes AMD64, Intel EM64T and so on.
Storage capacity
Main storage capacity = Number of storage units x Storage word length
For example, if MAR is 32 bits, the number of storage units is 2^32 = 4 x 1024 x 1024. If the storage word length is 8 bits, the storage capacity is 4 gigabytes (4 GB).
speed
Average number of instructions executed Per unit of time, Million Instruction Per Second (MIPS).
The system bus
Only one part can send information to the bus at a time, but more than one part can receive information because the bus is shared by all parts.
On chip bus
The connections within the chip, such as the connections between registers and between registers and ALU, etc.
The system bus
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Data bus: Two-way transmission, the number of which is called the data bus width. The data bus width is related to the machine word length and the memory word length. For example, if the bus width is 8 bits and the instruction word length is 16 bits, the CPU will need to access main memory twice to retrieve an instruction.
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Address bus: one-way transmission, indicating the address of the storage unit where the source or destination data resides on the data bus. The width of the address bus is related to the number of storage units. For example, in a 32-bit address bus, the number of addressable storage units in bytes is 2^32 = 4 x 1024 x 1024, that is, 4 Gigabyte.
When a word of data is read from memory, the CPU first sends its address through MAR to main memory through the address bus, and then sends read commands to main memory. After receiving the read command, the main storage will read the corresponding data and send it to MDR through the data bus. When writing a word of data to the memory, the CPU sends the destination address to main memory through the ADDRESS bus through the MDR, sends the data to the MDR, and then sends a write command to main memory. After receiving the write command, the main memory can write the data in the MDR to the destination address via the data bus:
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Control bus: decision bus access, used to send various control signals. The I/O device sends bus requests to the CPU, and the CPU sends read/write commands to the I/O device through the control bus.
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Communication bus: used for communication between computer systems or between computer systems and other systems (such as control instruments, mobile communications, etc.).
Virtual Storage System
In a virtual storage system, the programmer’s programming address range corresponds to the address space of the virtual storage. For example, if the machine instruction address code is 32 bits, the number of storage units of virtual memory can be up to 2^32 = 4 * 1024 * 1024. If the storage word length is 8 bits, the storage capacity is 4 Gegabyte, which may be much more than the actual number of storage units of main memory. This type of instruction address code is called a virtual address or logical address, and the actual address of main memory is called a physical address. The operating system (OS) is responsible for translating virtual addresses into physical addresses. For example, the Windows OS uses page headings and page tables to translate virtual addresses into physical addresses. If the virtual address is in main memory, it can be directly used by the CPU. Otherwise, the virtual address must be uploaded to main memory before it can be accessed by the CPU.
conclusion
Read the chapter on Binder Interprocess Communication system in Android Source Code Scenario Analysis, Luo (author of the original book) lists the reasons why Google developed Binder as an IPC framework: Binder interprocess communication improves efficiency and saves memory by copying data between processes only once compared to traditional interprocess communication mechanisms. Pipe also saves memory by copying data only once. (Twice, actually)
With Pipe (anonymous pipes, used for inter-process communication with affinity, such as the process of father and son, brothers process) as an example, the process A B to send data to the process, need to process A copy of data in the user space to pipeline (in kernel space), and then process B data copies from the pipeline to its own user space, The data was copied twice. With Binder, because virtual process address space (VM_area_struct) and virtual kernel address space (VM_struct) are mapped to the same physical memory space, when the Client and Server send data, The Client (as the data sender) copies the IPC communication data copy_FROm_user from its own process space to the kernel space, while the Server (as the data receiver) shares the data with the kernel. It no longer needs to copy the data, but obtains the memory address by the offset of the memory address space. Only one memory copy occurs. The most efficient is shared memory, which can be accessed without any copy but with a semaphore for information synchronization.
In order to understand why the maximum 32-bit CPU addressing space is 4G and Linux each process exclusive 3G user space, I took a look at the principles of computer composition.
It’s tiring to write an article, even if it’s just a summary. But if there’s a first, there’s a second. Read a lot of articles before, no summary record, a long time, all forget…
reference
[1] Tang Shuofei, Computer Composition Principle, Higher Education Press, 2000-7
[2] Yang Shengli and Liu Hongtao (Eds.) ARM Embedded Architecture and Interface Technology, Posts and Telecommunications Press, 2013-9
[3] Scenario Analysis of Android Source Code. Luo Shengyang, Publishing House of Electronics Industry
[4] Gityuan with Binder Driver