@[TOC]

Introduction to computer systems

Read a book read a book, is the text, (want to get high marks) more understanding

2. Representation and operation of data

Various bases and their conversions

Into the system	For example,
Binary: 0,1	Binary: 101.1 — > 1 × 2! 0 × 2″ + 1 × 2# + 1 × 2%” = 5.5
Octal: 0,1,2,3,4,5,6,7	Octal: 5.4 — > 5 × 8# + 4 × 8%” = 5.5
Decimal: 0,1,2,3,4,5,6,7,8,9	Decimal: 5.5 – > 5 × 10# + 5 × 10%” = 5.5
Hex: 0,1,2,3,4,5,6,7,8,9, A, B, C, D, E, F	Hex: 5.8 – > 5 x 16# + 8 x 16%” = 5.5
## Common way of writing in various bases

Binary superiority

② 0,1 correspond exactly to the logical values false and true. ③ It is convenient to use logic gate circuit to realize arithmetic operation

Arbitrary base → decimal

Using r base counting method, the cardinal number of each digit × the power of the base weight can be added in turn

R-base counting

== Base == : The number of different symbols used for each digit bit. Base R is r

For example,

Into the system	Calculation example
Binary: 1 0 0 1 0 0 1 0 1 1 0	1 * 2 ^ 7 + 1 * 2 ^ 4 + 1 * 2 * 2 ^ – ^ 1 + 1 1 + 1 * 2 ^ 2 = 146.75
Octal: 251.5	2 * 8^2 + 5 * 8^1 + 1 * 8^0 + 5 * 8^-1 = 168.625
Hexadecimal value: AE86.1	10 * 16^3 + 14 * 16^2 + 8 * 16^1 + 6 * 16^0 + 1 * 16^-1 = 44678.0625

You can also remember the common decimal values of binary bits (right click to save photo collection)

Binary ↔ octal, hexadecimal

Binary – > octal

Each group of 3 bits is converted to the corresponding octal symbol

Octal – > binary

Each octal number corresponds to a 3-bit binary number

Binary – > hexadecimal

Each group of 4 digits is converted to the corresponding hexadecimal symbol

Binary – > hexadecimal

Each group of 4 digits is converted to the corresponding hexadecimal symbol

Decimal to arbitrary base system

Mod inversion by division by x (x stands for base number)

For the full content, see this answer:Zhidao.baidu.com/question/37… For example: 75.3 decimal part =0.3So let’s convert to binary and that’s it

• The integer part

– Decimal part

Decimal → binary (piecing method)

I’m going to use this graph right here

Truth value and number of machines

• Truth value: a number consistent with human custom
• Machine number: The form in which the numbers are actually stored in the machine, and the signs need to be “digitized”

Take the following two numbers

Examples of fixed point and floating point numbers

	For example,
Fixed point number: the position of the decimal point is fixed	Eg: 996.007 — regular count
Floating point: The position of the decimal point is not fixed	Eg: 9.96007*102 — Scientific notation

Unsigned number

concept

== Unsigned number == : All binary bits of the entire machine word length are numeric bits, no sign bits, equivalent to the absolute value of the number.

Such as:

Said the scope of

An 8-bit binary number has 2^8 different statesThe unsigned number of n bits ranges from 0 to 2^ n-1

A signed number

The representation of a signed number

For example,But then the decimal point is not fixed, and this is how we feel when we’re dealing with all of our data that is not fixed in decimal places

So there is a specification for the fixed point representation of signed numbers

A fixed point representation of a signed number

Fixed integer

Fixed-point decimal

Note:

• Fixed-point integers and decimals can be expressed in three ways: source code, inverse code and complement code.

• Fixed-point integers can also be represented by shifting codes.

• If the truth value is X, [x] original, [x] inverse, [x] complement and [x] shift represent the corresponding source code, inverse code, complement code and shift code of the truth value respectively

Source code, inverse code, complement code, shift code

The original code

Radix-minus-one complement

• If the sign bit is ==0==, the == inverse code is the same as the source code ==

• If the sign bit is ==1==, the value bits of == are all reversed ==

complement

• The complement of a positive number = the source
• The complement of a negative number = the last bit of the inverse +1 (carry is considered)
• The negative complement is converted back to the original code in the same way: the mantissa is reversed and the last digit is +1

frameshift

• Shift: Invert sign bits on the basis of complement.

Note: Shift codes can only be used to represent integers

Fixed-point integers are represented in several codes

The truth value of the various codes is 0

	[+ 0]	[0]
The original code	[+ 0] = 00000000	[-0]原=10000000
Radix-minus-one complement	[+ 0] = 00000000	[-0]反=11111111
complement	[+0] complement = [-0] Complement = 00000000	[+0] complement = [-0] Complement = 00000000
Radix-minus-one complement	[+0] Shift = [-0] Shift = 10000000	[+0] Shift = [-0] Shift = 10000000

Various code conversion diagrams

Various codes represent ranges

Arithmetic shift operation

Shift: by changing the relative position of each digit and the decimal point, thus changing the weight of each digit. Multiplication and division can be realized by shift operation

Arithmetic shift of source code

For example, the source code is10101000Arithmetic shiftThe arithmetic shift of the source code — the sign bits of == remain unchanged, and only the numeric bits are shifted. = =

• Right move: 0 is added in high position and 0 is discarded in low position. If the discarded bit =0, it is equivalent to ÷2; If the discarded bit ≠0, the precision will be lost
• Left shift: 0 is added at low level and 0 is discarded at high level. If the discarded bit =0, it is equivalent to ×2; If the discarded bit ≠0, there will be a serious error

Arithmetic shift of inverse code

The arithmetic shift of the inverse code — == The inverse of the positive code is the same as the original code, so is the shift operation for the positive and inverse code. = =

• Right move: 0 is added in high position and 0 is discarded in low position.
• Left shift: 0 is added at low level and 0 is discarded at high level

The arithmetic shift of the inverse code — == The numeric bits of the negative code are the opposite of the original code, so the shift operation of the negative code is as follows, ==

• Right move: 1 for high, 1 for low.
• Move to the left: add 1 at the low level and discard at the high level.

The arithmetic shift of the complement

The arithmetic shift of the complement — == The complement of a positive number is the same as the original, so the shift operation on the positive complement is the same as the original. = =

• Right move: 0 is added in high position and 0 is discarded in low position.
• Left shift: 0 is added at low level and 0 is discarded at high level.

The arithmetic shift of the complement — == negative complement === the last bit of the inverse +1 causes the consecutive ones on the rightmost side of the inverse to become zeros due to carry, until the carry hits the first zero.

Rule — == in the negative complement, the rightmost 1 and its right are the same as the original code. The arithmetic shift rule for the negative complement is as follows:

• Right move (same as inverse code) : high fill 1, low discard.
• Left shift (same as the original code) : 0 is added in the low position and discarded in the high position.

Logical shift

• Logic to the right: high fill 0, low discard.
• Logic moved to the left: 0 is added at the lower level and discarded at the higher level.

A logical shift can be thought of as an arithmetic shift on an “unsigned number”

Examples of logical shift applications

For example, color RGB stores R = 102 01100110 G = 139 10001011 B = 139 10001011

Three gray values need to be combined into a color image

Cyclic shift

The addition and subtraction of the source code

Source code addition:

1. Plus + plus → Absolute values add up to be positive (may overflow)
2. Negative + negative → Absolute values add up to be negative (may overflow)
3. Plus plus minus minus minus, the sign is the same as the number with the highest absolute value
4. Minus plus plus minus big minus small, sign the same as big

The subtraction operation of the original code, the “subtraction” sign is reversed and converted to addition:

• Plus minus minus plus plus plus
• Minus, plus, minus, plus minus
• Plus minus plus minus plus minus
• Minus plus plus minus minus minus

The addition and subtraction of the complement

For the complement, whether addition or subtraction, will eventually change to addition, by the adder to implement the operation, sign bit also participate in the operation.

Supplement:

1. [B] to fill

[-b] complement: [B] complement with the sign bit plus 1

2. Negative numbers complement → original:

(1) The numeric digit is inverse +1; ② In the negative complement, the rightmost 1 and its right are the same as the original code. The left-hand side of the rightmost 1 is the same inverse

sample

Let’s first look at an example: set the machine word length as 8 bits (including 1 sign bit), A = 15, B = -24, find [A+B] complement and [A−B] complement

So let’s figure out the original complements of A and B

[A+B] complement = [A] complement + [B] complement = 0 0001111 + 1,1101000 = 1,1110111

Source code: 1,0001001 True value -9

[a-b] complement = [A] complement + [-b] complement = 0 0001111 + 0 0011000 = 0 0100111 truth value +39

Where C = 124, calculate the complement of [A+C] and [B−C], and calculate the complement of [B−C] according to the above method: [A+C] complement = 0 0001111 + 0 1111100 = 1,0001011 truth -117 overflow [B−C] complement = 1,1101000 + 1,0000100 =0,1101100 truth +108

Overflow judgment

Overflow condition

• Only “plus plus” will overflow — plus plus = minus
• Only negative + negative overflows — negative + negative = positive

Overflow judgment: use double sign bit

The positive sign is 00, The negative sign is 11 [A+C] complement = 00,0001111 + 00,1111100 == =01==,0001011 overflow [B−C] complement = 11,1101000 + 11,0000100 == =10==,1101100 underflow

Let the two sign bits be S1, S2, then V=S1 xor S2

• If V=0, there is no overflow.
• If V=1, an overflow occurs.

The idea of multiplication

Multiplication by hand (binary)

For example, calculate 0.1101 x 0.1011

Column vertical

A shift

A one-digit multiplication of the source code

Addendum: Knowledge of arithmetic machine

Arithmetic unit: used to perform arithmetic operations (e.g., addition, subtraction, multiplication and division), logical operations (e.g., and or not)

• ACC: accumulator, used to store operands, or operation results.
• MQ: multiplier register, used to store operands or operation results during multiplication and division operations.
• X: Generic operand register for storing operands
• ==ALU== : Arithmetic logic unit, which implements arithmetic and logic operations through complex internal circuits

	add	Reduction of	take	In addition to
ACC	The addend and the sum	Minuend, difference	The product high	Dividend, remainder
MQ			Low value of multiplier or product	shang
X	addend	reduction	multiplicand	divisor

Source code one bit multiplication method: first add and then shift, repeat N times

The sign bit is determined by == xor ==; The numerical part is done by n rounds of addition and shift of the multiplicand and the absolute value of the multiplicand according to the bit of the current multiplier involved in operation (ACC) to determine what to add.

1. If the current operation a = 1, (ACC) + [| | x] original;
2. If current operand bit =0, (ACC)+0.

After each round of addition, the contents of ACC and MQ move to the right logically

Hand is simulated

tips

• The sign bit of the multiplier is not involved in the operation and can be omitted
• The source code can be multiplied by a single sign bit only
• When answering questions, the final result had better be written as the original number of machines

sample

Set the machine word length as 5 bits (including 1 sign bit, n=4), x = −0.1101, y = +0.1011, and use the original code multiplication to find x·y

Solution: The manual calculation looks like thisSign bit: 0 is obtained by xOR operation of 1 and 0.

So the subsequent result is: ==x·y= -0.10001111==

One-digit Multiplication of complement (Booth algorithm)

1. Do n rounds of addition, shift, and finally do one more addition
2. Each addition may be +0, +[x] complement, +[-x] complement
3. Each shift is an arithmetic shift to the right of the complement.
4. Sign bits participate in operations

In the second step, you need to determine what to add based on the lowest, secondary bit in MQ:

• Auxiliary bit – lowest bit of MQ = 1, (ACC)+[x] complement
• Auxiliary bit – lowest bit of MQ = 0, (ACC)+0
• (ACC)+[-x] complement when the lowest value of auxiliary bit -MQ = -1

Hand is simulated

sample

Set the machine word length as 5 bits (including 1 sign bit, n=4), x = −0.1101, y = +0.1011, and use the Booth algorithm to find x·y

Solution: The manual calculation looks like thisThe last too[x·y] complement = 11.01110001 that is x·y = −0.10001111

Conclusion to solve the problem.

1. N round addition, arithmetic right shift, the addition rule is as follows:

(ACC)+[x] complement auxiliary bit – MQ minimum = 1, (ACC)+[X] complement auxiliary bit – MQ minimum = 0, (ACC)+0 auxiliary bit – MQ minimum = -1, (ACC)+[-x] complement 2. The arithmetic right shift of the complement: the sign bit does not move, the value bit moves right, the positive number moves right to fill 0, and the negative number moves right to fill 1 (whatever the sign bit is) 3. Generally speaking, the multiplier and partial product of Booth algorithm adopt double sign bit complement

The comparison of the primary and complement bits of multiplication

Source code one bit multiplication:	Complement bit multiplication:
Do n rounds of addition and shift	Do n rounds of addition, shift, and finally do one more addition
Each addition might be+ 0, ` + [	x
Each shift is a logical right shift.	Each shift is an arithmetic shift to the right of the complement.
The sign bit does not participate in the operation	Sign bits participate in operations
# Recovering the remainder of division
Thinking diagram (typing is not clear is)

Supplementary knowledge: size – end patterns with boundaries on them

Big and small end mode

You must know that multi-byte data must occupy several consecutive bytes in memory

The most significant byte is MSB and the least significant byte is LSB

For example,

• Big-endian mode is easier for humans to read

• Small – end mode is more machine – friendly

  

Boundary alignment

Modern computers are usually addressed by byte, that is, one address per byte is usually also supported by word, half-word, and byte addressing. If the storage word length is 32 bits, 1 word equals 32 bits, and half word equals 16 bits.

Each access can read/write only 1 character

1. Here’s how the boundary pairs work: anything less than four bytes will be filled with empty space

2. Below are the unaligned, unpadded values that are less than four bytes

The representation of floating point numbers

Fixed-point numbers: pure decimal 0.1011 and pure integer 11110

Floating-point representation

== Order code == : fixed-point integer represented by common complement or shift code == Mantissa == : fixed-point decimal represented by common source code or complement code

True values of floating point numbers:

The order E represents a floating point numberSaid the scope ofAnd the actual position of the decimal point; The mantissa of M reflects the number of bits nThe precision of a floating point number.

Take a chestnut

Example: order code, mansa are expressed by complement, find the truth value of a, b a = 0,01; 1.1001 b = 0, 10; 0.01001

Solution: a: the order code 0,01 corresponds to the truth value +1 mantis 1.1001 corresponds to the truth value -0.0111

The truth value of a = 2^1^×(−0.0111) = −0.111 == (equivalent to moving the mantissima decimal to the left or the decimal to the right) ==

B: order code 0,10 corresponds to truth value +2 mantras 0.01001 corresponds to truth value +0.01001

The truth value of b = 2^2^×(+0.01001) = +1.001 ==

Normalization of the mantissa of a floating point number

Normalized floating point: Specifies that the highest numeric bit of the mantissa must be a valid value.

Go left and go right

• Left gauge: Normalize when the result of floating-point operation is normalized, move the mantissa arithmetic to the left one bit, and decrease the order code by 1.

• Right gauge: When the mantissa overflow (double sign bit 01 or 10) occurs in the result of floating-point operation, the mantissa arithmetic is moved one bit to the right and the order code is increased by 1.

To put it bluntly:

• To return to the left is to normalize by arithmetically moving to the left and reducing the order code by 1

• Right normalization is normalized by arithmetically moving right and adding 1 to the order code

Example: floating point addition

Example: A = 010; 00.1100, b = 010; 00.1000, a + b

Solution: A = 2 ^ ^ 2 x 00.1100, B = 2 ^ ^ 2 * 00.1000 = a + b ^ 2 ^ 2 * 00.1000 = 00.1100 + 2 ^ 2 ^ 2 ^ ^ 2 * (00.1100 + 00.1000) = 2 ^ 2 ^ ^ ^ 3 * 00.1010 * 01.0100 = 2

(Note: use “double sign bit”, when overflow occurs, can be saved. The higher sign bit is the correct sign bit)

Normalize the characteristics of floating point numbers

1. Normalization of mantissa represented by original code:

• Positive number is 0.1 x… In the form of ×, its maximum value is 0.11… 1; The minimum value is 0.10… 0.

The mantissa ranges from 1/2≤M≤(1−2^− N ^).

• A negative number is 1.1 x… The maximum value is 1.10… 0; The minimum value is 1.11… 1.

The mantissa ranges from −(1−2^− N ^)≤M≤−1/2.

2. Normalization of mantissa represented by complement:

• Positive number is 0.1 x… In the form of ×, its maximum value is 0.11… 1; The minimum value is 0.10… 0.

The mantissa ranges from 1/2≤M≤(1−2− N).

• A negative number is 1.0 x… In the form of ×, its maximum value is 1.01… 1; The minimum value is 1.00… 0.

Mantissa ranges from −1≤M≤−(1/2+2− N)

3. Scope

4. Notes (※)

1. The mantissa of normalized source code, the highest value bit must be 1

2. The mantissa of the normalized complement, the sign bit must be opposite to the highest value bit

3. The complement code is moved arithmetically to the left, and the low value is 0; The complement is shifted to the right

The addition and subtraction of floating point numbers

We can start by analogizing binary by the decimal floating-point addition and subtraction steps

Decimal floating-point number addition and subtraction operation steps:

Floating point number addition and subtraction operation consists of five steps: ① order, ② mantissa addition and subtraction, ③ normalization, ④ rounding, ⑤ overflow

For example, calculate 9.85211 x 10^12^ + 9.96007 x 10^10^

Solution:

The addition and subtraction of binary floating-point numbers

We did the decimal floating-point addition and subtraction above, and we can do the same with the following five steps

Let’s look at an example: given the decimal numbers X=−5/256 and Y=+59/1024, X−Y is calculated according to the machine’s complement floating-point operation rules. The result is expressed in binary format as follows: == takes 2 bits of the rank code, 3 bits of the rank code, 2 bits of the number character, and 9 bits of the mantras ==

Solution:

First we use the complement to represent the order and mantissa,

5D = 101B, 1/256 = 2^-8^ → X = -101 × 2^-8^ = -0.101 × 2^-5^ = -0.101 × 2^-101^ -59d = 111011B, 1/1024 = 2 ^ – ^ – > Y = 10 + 111011 * 2 ^ – ^ = 10 + 0.111011 * 2 ^ – ^ 4 = + 0.111011 x ^ ^ 2-100

And then converted to the complement form X: 11011,11.011000000 == (X is negative to complement the negative +1 mantras of order code are the same operation) == Y: 11100,00.111011000

1. To order

Make the order codes of the two numbers equal, the small order equals the large order, and the mantissa moves to the right by one, and the order code is increased by 1

[δ E] complement =11011+00100=11111, know δ E=−1 ② order: X: 11011,11.011000000 → 11100, 11.101100000 X = -0.0101 × 2^-100^

2. Mantissa plus and minus

-y: 11100,11.000101000 ==

And then we have X plus minus Y

	11.101100000
+ 	11.000101000
	10.110001000
Copy the code

So x-y: 11100, 10.110001000

3. The normalized

X-Y：11100, 10.110001000 à 11101,11.011000100

4. Rounding

There is no rounding

5. To overflow

Constant order code, no overflow, the truth value of the result is 2−3 x (−0.1001111)2

Addition and subtraction of floating point numbers – rounding rules

“0” rounding “1” method:

It is similar to the rounding method in decimal number operation, that is, when the mantissa moves right, the highest numeric bit removed is 0, then it is removed; The highest numeric bit removed is 1, and 1 is added to the last mantissa. Doing so may cause the mantissa to overflow again, in which case you need to do the right gauge again.

Constant “1” method:

When the mantissa is moved to the right, the last mantissa after the right move is always set to “1” regardless of whether the highest value bit lost is “1” or “0”. This method also has two possibilities of making the mantissa larger and smaller.

For example,

Cast casting

Operability of transformation

Char → int → long → double float → double int → float: Possible loss of precision float → int: possible overflow and loss of precision

Conclusion: There is no loss in the conversion process

Int: indicates an integer ranging from -2^31^ to 2^31^-1. 32 significant digits Float: indicates an integer ranging from ±[2^-126^ ~ 2^127^×(2−2^−23^)]. 23+1=24 digits

Parity check code

concept

A word consisting of several bits of code is called the == code word ==. When two code words are compared bit by bit, the number of different bits is called == Distance between two code words ==. A coding scheme may have several legal code words, and the minimum distance between the legal code words is called “== code distance ==”. For example: The following two groups of spacing are 1 and 2 respectively

Where the capability range of == code spacing == is:

• When d=1, there is no error detection ability;
• When d=2, it has error detection ability;
• When D ≥3, if the design is reasonable, it may have error detection and error correction ability

Parity check code

• Odd check code: The number of 1s in the whole check code (valid information bits and check bits) is odd.
• Parity code: The number of 1s in the whole parity code (valid bits and parity bits) is even.

Example 1: Give two parity check codes 1001101 and 1010111. If the highest bit is the parity bit and the remaining seven bits are the information bits, the corresponding parity check code is: Parity: 11001101 01010111 Parity: 01001101 11010111

1 0

Example 2: Give two parity check codes 1001101 and 1010111. If the highest bit is the parity bit and the remaining seven bits are the information bits, the corresponding parity check code is: Parity: 11001101 01010111 Parity: 01001101 11010111

Parity check hardware implementation: each information xOR (module 2 plus) operation, the result is parity bits

For example: take the parity bits of the above example:

An even number of errors cannot be checked

For example,

conclusion

Main memory

Reserve, I seem to have not learned, do not know, may be mixed with the back storage system, read a book first

Instruction system

Directive case article (must see) : editor.csdn.net/md/?article…

The structure of modern computers

Let’s get the controller on this one!

Learn to command system can be more diligence before make the typical process: yangyongli.blog.csdn.net/article/det…

Instruction format

Definition of instruction

== instruction (also known as machine instruction) == : a command that instructs a computer to perform an operation. It is the smallest functional unit of computer operation.

The set of all the instructions of a computer constitutes the instruction system of the machine, also known as == instruction set ==.

Note: a computer can only execute the instructions in its own instruction system, not the instructions of other systems.

For example, x86 and ARM architectures cannot execute each other’s instructions.

Instruction format

An instruction is a statement in machine language, a meaningful set of binaries.

An instruction usually includes two parts: opcode field and address code field (as shown in the figure below) :

The == opcode == is what the user wants to do. For example: downtime interruption, reverse repair, addition, subtraction, multiplication and division… .

== address == is just saying who do you operate on? For example: no operation object, one operation object, two operation objects… .

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An instruction may contain zero, one, two, three, four address codes…

According to the number of address code, the instruction can be divided into zero address instruction, one address instruction, two address instruction…

Zero address instruction

1. Operands are not required, such as empty operation, stop, off interrupt instructions
2. In a stack computer, the two operands are implicitly stored at the top and subtop of the stack, and the result is pushed back to the top of the stack

One address instruction

1. Only single operands are required, such as addition 1, subtraction 1, negation, complement, etc

Instruction meaning: OP(A1)→A1, 3 times of access are needed to complete an instruction: fetching finger → reading A1 → writing A1 2. Two operands are needed, but one of the operands is implied in a register (such as in ACC) instruction meaning: (ACC)OP(A1)→ACC, it takes two accesses to complete an instruction: fetching finger → reading A1

Note: A1 refers to a main memory address, and (A1) refers to the contents of the address to which A1 points

Two, three address instruction

== is often used for arithmetic operations that require two operands, and for logical operations related instructions ==

Instruction meaning :(A1)OP(A2)→A1 to complete an instruction, it needs to access 4 times, fetching finger → reading A1→ reading A2→ writing A1

== is often used for arithmetic operations that require two operands, and for logical operations related instructions ==

Instruction meaning :(A1)OP(A2)→A3 to complete an instruction, it needs to access 4 times, fetching finger → reading A1→ reading A2 → writing A3

Four address instruction

Instruction meaning :(A1)OP(A2)→A3, A4= address of the next instruction to be executed

To complete an instruction, it is necessary to access 4 times, fetching finger → reading A1 → reading A2 → writing A3

Under normal circumstances: after the instruction, PC+1 points to the next instruction four address instruction: after the execution of the instruction, change the value of PC to the address indicated by bit A4

Xiao Yang said: There are so many things!

What is the effect of the number of digits in the address code?

The direct addressing range of the n-bit address code =2^n^, == If the total length of the instruction is fixed, the more the number of address codes, the worse the addressing capability ==

classification

Instruction – Sorted by number of address codes

Instructions – Sorted by instruction length

Can be divided into: half word long instruction, single word long instruction, double word long instruction – instruction length is the machine word long how many times

== Instruction word length == : Total length of an instruction (subject to change) == Machine word length == : Number of bits of binary data that can be processed by the CPU in a single integer operation (usually directly related to ALU) == Storage word length == : Number of bits of binary code in a storage cell (usually the same as MDR bits)

The length of the instruction word affects the time required to fetch the instruction. For example: machine word length = storage word length =16bit, then take a double word length instruction need two access

Fixed-length instruction word structure: all instructions in an instruction system are of equal length. Variable length instruction word structure: all instructions in an instruction system are of unequal length

Instructions – Sorted by opcode length

1. Fixed-length opcodes: Opcodes of the same length for all instructions in the instruction system (n bits → 2^n^ instructions)

— Decoding circuit design of controller is simple, but flexibility is low 2. Variable-length opcode: the opcode length of each instruction in the instruction system is variable — decoding circuit design of controller is complex, but flexibility is high 3. Extended opcode instruction format: fixed-length instruction word structure + variable length opcode

Instructions – Classified by operation type

1. Data transfer (== Data transfer class: data transfer between main memory and CPU ==)

LOAD: puts data from a register (source) into a register (destination). STORE: Puts data from a register (source) into a STORE (destination)

2. Arithmetical logic operation

Arithmetic: add, subtract, multiply, divide, add 1, subtract 1, complement, floating point operation, decimal operation logic: and, or, not, xOR, bit operation, bit test, bit clearance, bit inversion 3. Shift operations Arithmetic shift, logical shift, circular shift (with and without carry) 4. Transfer operation (== program control class: change the order of program execution ==) Unconditional transfer JMP conditional transfer JZ: result is 0; JO: Result overflow; JC: Results have carry calls and RETURN CALL and RETURN traps and Trap instructions 5. Input/output operations (== INPUT/output (I/O) : data transfer between the CPU and I/O device ==) Data transfer between the CPU register and THE I/O port (the port is the register in the I/O interface)

Instruction format summary

Extended opcode

The instruction consists of an operation code and several address codes.

PS: First review the concept of instruction word structure and opcodes:

• Fixed-length instruction word structure: All instructions in an instruction system are of equal length
• Variable-length instruction word structure: The varying lengths of instructions in an instruction system

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• Fixed-length opcodes: The opcodes of all instructions in an instruction system are of the same length
• Variable length opcode: The variable length of the opcodes in the instruction system

Fixed length instruction word structure + variable length opcode → Extended opcode instruction format (== that is, instructions with different address numbers use different lengths of opcodes ==)

Examples of extended opcodes

This is just one design approach:

Note the following when designing extended opcodes:

1. A short code is not allowed to be a prefix of a long code, that is, the short opcode cannot be the same as the previous part of the long opcode. (== contrast Huffman tree “prefix encoding” ==)
2. The opcodes of each instruction must not be repeated.

In general, short opcodes are assigned to instructions that are used more frequently. For infrequently used instructions, longer opcodes are assigned to minimize instruction decoding and analysis time.

Design extended opcodes

Let the instruction word length be fixed at 16 bits, and try to design an instruction system that meets the following requirements: a) there are 15 three-address instructions b) there are 12 two-address instructions c) there are 62 one-address instructions d) there are 32 zero-address instructions

Let the address length be N, and m states are reserved for the upper layer, and M x 2 states can be extended for the lower layer! Kind of state

Solution: a) a total of 2^4^=16 states set aside 16-15=1

B) a total of 1 ×2^4^=16 types set aside 16-12=4 types

C) a total of 4 ×2^4^=64 sets aside 64-62=2

D) a total of 32 kinds of 2 ×2^4^=

	0000-1110.	A1(Legal range taken)	A2	A3
1111 XXXX XXXXXXXX	1111	0000-1011.	A1	A2
1111 11XX XXXX XXXX	1111	1100-1110. 1111	0000-1111. 0000-1101.	A1
1111 1111 111X XXXX	1111	1111	1110-1111.	0000-1111.

Instruction opcode

The == opcode == indicates in the instruction what kind of operation and function the instruction should perform.

== Opcode == is the key information == to identify the instruction, understand the function of the instruction and distinguish the composition and use method of the address content of the operand. For example, to indicate whether arithmetic is added or subtracted; Program transfer or return operation.

Opcode classification:

Fixed-length opcodes:

== Allocates a fixed number of bits (fixed length) to represent the opcode in the highest bit portion of the instruction word. = =

• General n – bit opcode field instruction system can represent a maximum of 2^ N ^ instructions.
• Excellent: fixed-length opcodes for simplifying computer hardware design, improve instruction decoding and recognition speed is very beneficial; – Missing: As the number of instructions increases, it takes up more fixed bits, limiting the number of bits that represent the address of the operand.

Extended opcodes (variable opcodes) :

== The number of bits in the opcode field of all instructions are not fixed and are scattered in different positions of the instruction word. = =

• The most common method of varying the length of an opcode is to extend the opcode so that the length of the opcode increases as the number of addresses decreases

The instruction can have opcodes of different lengths, which can effectively shorten the instruction word length on the premise of satisfying the needs.

• Excellent: keep relatively rich instruction types under the premise of limited instruction word length;
• Lack: increases the difficulty of instruction decoding and analysis, complicates the design of the controller.

First, let’s remember how computers work:Yangyongli.blog.csdn.net/article/det…

Instruction addressing

= = instruction addressing = =, = = = = next to execute commands = = = = = = = = address (always given by the program counter (PC))

(PC) + 1→ PC, as shown in the example below

The system uses the == fixed-length instruction word structure == instruction word length = storage word length =16bit=2B (address is 16 bits) main memory == address by word ==

We split the above example into instruction address, opcode and address code. As shown below

Sequential addressing

(PC) + 1 → PC

Jumping addressing

Indicated by the transfer instruction

JMP: Unconditional transfer Change the content in the PC to address code value

O ha ha ~ O (studying studying)

For example, in the previous example

summary

Instruction addressing v.S. data addressing

Different addressing modes

Addressing mode features include :(ten)

Data addressing

We add four bits to the original addressing mode, that is, the == addressing characteristic == (which tells the following formal address how to read), and we make == data addressing ==.

An address instruction form:

Finally, a valid address is obtained after reading (find the real address of the operation number, called == effective address (EA)==).

Two address instruction form:

The following addressing conditions: Assume instruction word length = machine word length = storage word length, assume operand 3

Ten ways of addressing

Direct addressing

Indirect addressing

Register addressing

Register indirect addressing

Implied addressing

Addressing immediately

Offset addressing

Too much content: please move driving another blog: yangyongli.blog.csdn.net/article/det…

Stack addressing

Too much content: please move driving another blog: yangyongli.blog.csdn.net/article/det…

Summary of data addressing

CISC vs. RISC

	CISC: Complex Instruction Set RISC:	RISC： Reduced Instruction Set Computer
analogy	C language with many library functions	C without library functions
Design ideas	A single instruction performs a complex basic function.	A command to complete a basic “action”; Multiple instructions combine to perform a complex basic function.
	CISCIdeas: in addition to provide integer addition, subtraction and multiplication instructions in addition, also provide matrix addition instructions, matrix subtraction instructions, matrix multiplication instructions	RISCProvide only integer addition, subtraction and multiplication instructions
On behalf of	The x86 architecture is mainly used for notebook and desktop computers	ARM architecture, mainly used in mobile phones, tablets, etc
Instruction and circuit	An instruction can be done by a special circuit	One instruction per circuit, the circuit design is relatively simple, lower power consumption
implementation	Some complex instructions with pure hardware implementation is very difficult to use the “stored program” design idea, by a more general circuit with storage components to complete an instruction	“Parallel”, “pipeline”

Divide the above into smaller pieces, as shown in the table below

Take a chestnut

For example, if you forget the previous schematic of how a computer works, you can click on the link below to see it again:Blog.csdn.net/weixin_4552… Among them, the multiplication instruction can access, which must be CISC

Central processing unit

The function of the CPU

1. Command control. Perform the operations of fetching, analyzing and executing instructions, that is, sequence control of programs.
2. Operational control. The function of an instruction is often realized by a combination of several operational signals. CPU tube

And generate the operation signal of each instruction out of the memory, send various operation signals to the corresponding parts, so as to control these parts according to the requirements of the instruction. 3. Time control. Time control of various operations. Time control to provide each instruction with the appropriate control signal in chronological order. 4. Data processing. Perform arithmetic and logical operations on data. 5. Interrupt processing. To deal with the abnormal situation and special request in the process of computer operation.

Function of arithmetic unit and controller

• == Arithmetic unit == : Data processing
• == Controller ==

Coordinate and control the instruction sequence of each part of the computer to execute the program. The basic function includes fetching instruction, analyzing instruction and executing instruction

- Fetch instruction: automatically form instruction address; Automatically issue the command to fetch the command. - Analysis instruction: opcode decoding (analyze what operation to be completed by this instruction); - Generates the valid address of the operand. - Execution instruction: According to the "operation command" and "operand address" obtained from the analysis instruction, the operation signal control sequence is formed to control the arithmetic unit, memory and I/O device to complete the corresponding operation. - Interrupt processing: management bus and I/O; Handle exceptions (such as power failures) and special requests (such as a printer request to print a line of characters)Copy the code

More vividly, as shown below:

Basic structure of arithmetic unit

Arithmetic unit includes: == arithmetic logic unit and general purpose register group. = =

1. == Arithmetic logic unit == : The main function is to perform arithmetic/logical operations.
2. == General register group == : Such as AX, BX, CX, DX, SP, used to store operands (including source operands, destination operands, and intermediate results) and various address information. SP is the stack pointer that indicates the address at the top of the stack.

For example, the following picture :(of course, it is not so simple, this is only a schematic diagram, it is definitely not so simple, we can refer to it first)

Dedicated data path mode: the connection line is arranged according to the flow direction of data and address during instruction execution.

To explore problems

If directly connected by wire as shown above, it is equivalent to multiple registers simultaneously and continuously transferring data to ALU.

That affirmation is not line ah, such data not transmission chaos, so how do we solve?

Solution 1. Use a multiplexer

Select one output according to the control signal

Solution 2. Use three-state gate

Can control the output of each path as follows:

R0out for1, the data in R$is output to A, and R0out is0The data in R$cannot be output to ACopy the code

Advantages and disadvantages: High performance, almost no data conflict phenomenon, but complex structure, large amount of hardware, difficult to achieve.

The real basic structure of an algorithm

The CPU uses internal single-bus mode: == All inputs and outputs of registers are connected to a common path. = =

1. == Arithmetic logic unit == : The main function is to perform arithmetic/logical operations.
2. == General register group == : Such as AX, BX, CX, DX, SP, used to store operands (including source operands, destination operands, and intermediate results) and various address information. SP is the stack pointer that indicates the address at the top of the stack.
3. == Temporary register == : Used to temporarily store data read from main memory. This data cannot be stored in a universal register or its original contents will be destroyed.
4. == Cumulative register == : It is a general purpose register that temporarily stores the result information of ALU operations for addition operations.
5. == Program state word register == : Reserve various state information established by the result of arithmetic logic operation instruction or test instruction, such as overflow flag (OP), symbol flag (SF), zero flag (ZF), carry flag (CF), etc. These bits in the PSW are involved in and determine the formation of microoperations.
6. == shifter == : Shifts the result of the operation.
7. == counter == : Controls the number of steps in multiplication and division operations.

The advantages and disadvantages

The structure is simple and easy to implement, but there are many conflicts in data transmission and the performance is low.

Basic structure of controller

1. Program counter: Used to indicate the location of the next instruction in main memory. The CPU goes to main memory to fetch instructions according to the contents of the PC. Because the instructions in the program are (usually) executed sequentially, the PC has auto-increment.
2. Instruction register: Used to hold the instruction currently being executed.
3. Instruction decoder: Decodes only opcode fields to provide specific operation signals to the controller.
4. Microoperation signal generator: according to IR content (instruction), PSW content (state information) timely sequence signal, generate control signals required by the entire computer system, its structure has two types of combination logic and storage logic.

5. Timing system: Used to generate various timing signals, which are obtained by unified CLOCK division. 5. Memory address register: Used to store the address of the main memory unit to be accessed. 6. Memory data register: Used to store information written to or read from main memory.

Our above computer and controller combine to form a CPU.

The basic structure of the CPU

We will note that the ALU register CU interrupts the system like this.

summary

Instruction cycle

== Instruction cycle == : The total time required for the CPU to fetch and execute an instruction from main memory. Instruction cycles are often expressed in terms of machine cycles, also known as CPU cycles

A machine cycle consists of several clock cycles (also known as beats, t-cycles, or CPU clock cycles, which are the most basic unit of CPU operation).

The number of machine cycles in each instruction cycle can be different, and so can the number of beats in each machine cycle. The following figure can be divided into fixed-length machine cycle and indefinite machine cycle. CLK: clock pulse

Several common instruction cycles

The number of machine cycles in each instruction cycle can be different, and so can the number of beats in each machine cycle.

Instruction cycle flow

There are CPU accesses in all four cycles, but the purpose of accesses is different.

1. Take the reference period for == take the instruction ==
2. The interval between addresses is for == to take the valid address ==
3. The execution period is for == to take the operand ==
4. Interrupt cycles are used to == save program breakpoints. = =

These four cycles are controlled internally by triggers

Trigger, can hold 1 binary bit.

The CLK (clock pulse) determines which cycle the instruction executes by judging the states of the four triggers. The specific status judgment is shown in the following figure

Instruction cycle data flow

Take refers to cycle

Step of finger cycle:

1. The current instruction address is sent to the memory address register.

(PC) → MAR 3. Send the contents of MAR in main memory to MDR by data bus, denoted as M(MAR) → MDR 2. CU sends control signal to main memory by control bus, here is read signal, denoted as 1 → R 4. Send the content in MDR (instruction at this time) to IR and write it as :(MDR) → IR 5. CU sends out control signal and forms the address of the next instruction, write it as :(PC)+1 → PC

The specific data flow diagram is as follows:

Addressing cycle between

Interval interval step:

1. Enter the address code of the instruction into MAR,

Ad(IR) → MAR or Ad(MDR) → MAR 2. CU sends a control signal and starts the main memory to do the read operation. Send the contents of main memory indicated by MAR to MDR via data bus, denoted as M(MAR) → MDR 4. Send the effective address to the address code field of the instruction, denoted as :(MDR)→ Ad(IR)

The specific data flow diagram is as follows:

The lifecycle

The task of the execution cycle is to generate the execution result through ALU operation according to the opcodes and operands of the instruction word in IR.

Different instructions operate in different execution cycles, so there is no unified data flow.

Interrupt cycle

== Interrupt == : Pauses the current task to complete another task.

To be able to resume the current task, you need to save the breakpoint. The breakpoint is usually stored on the stack, where SP is the address at the top of the stack.

Interrupt cycle steps:

1. CU control sends the modified address SP minus 1 to MAR

(SP)-1 → SP, (SP) → MAR: (SP)-1 → SP, (SP) → MAR: (SP)-1 → SP, (SP) → MAR Send the breakpoint (PC content) to MDR as :(PC) → MDR

4. CU controls the entry address that will interrupt the service program

(generated by the vector address forming component) into PC, denoted as: vector address → PC

The specific data flow diagram is as follows:

Instruction execution scheme

An instruction cycle usually consists of several periods (execution steps), each of which performs part of the instruction’s function, and several successive steps that perform all of the instruction’s function.

Plan 1. Single instruction cycle

Use the same execution time for all instructions.

== instructions are executed sequentially; = =

The instruction cycle depends on the execution time of the instruction with the longest execution time.

Disadvantages:

Using this longer cycle for instructions that could have been completed in less time would slow down the entire system.

Scheme 2. Multiple instruction cycle

Different execution steps are selected for different types of instructions.

== instructions are executed sequentially; = =

Different number of clock cycles can be selected to complete the execution of different instructions.

Disadvantages:

More complex hardware designs are required.

Plan 3. Pipeline scheme

Start one instruction per clock cycle, and try to have more than one instruction running simultaneously, but each in a different execution step.

== instructions are executed in parallel between ==

Like this

The summary of this chapter

Microprogrammed controller

(If I have time, I recommend reading, my version may not be the same as the one taught in school.)

Storage system

It’s all concepts. Read a book

Seven, IO (not learn, can’t)