Zhao Jiong; Linux Kernel Full Notes 0.11 revision V3.0

Principles of microcomputer composition

High-speed PCIE bus for serial communication point-to-point technology.

In order for different parts of the system to achieve their highest transmission speed, the bus structure is derived from two chipsets, north bridge and South Bridge.

  • Northbridge chip (high speed bus) : Interface with CPU, memory and AGP video.
  • Southbridge chip (low speed bus) : manage low and medium speed components, PCI bus, IDE hard disk interface, USB port.

I/O port addressing and access control mode

In order for the CPU to access data and state information on the I/O interface controller or control card, it needs to know their address (data port, command port, state port) — the port address, unified addressing (the port address in the I/O controller goes into the memory addressing address space, Accessing a port is the same as accessing memory) and independent addressing (separate the port address space, called the I/O address space, using specialized I/O instructions to access the port).

Interface access can be: program loop query mode, interrupt processing mode and DMA transmission mode.

  • Circular programming is used in the few places where the device or controller can return information immediately.
  • The interrupt handling mode needs the support of the interrupt controller.
  • Direct memory access DMA: Bulk data transfer between I/O devices and memory, requiring the use of a DMA controller without the intervention of the CPU.

Main memory, BIOS and CMOS memory

To be compatible with the original PC, the system uses the same physical memory as the original PC. For the memory larger than 1MB, there is a BIOS shadow area at the top end of the memory.

BIOS: used for computer boot execution system self-check; Set up the configuration table required by the operating system (interrupt direction table, disk parameter table…) ; Initialize the processor and the rest of the system; Provide hardware device interface services; For the sake of access efficiency, the Linux operating system does not use BIOS functions when running.

== Reset button pressed: CPU automatically sets CS:IP=0xF000:0xFFF0(0xFFFFFFF0), segment base address 0xFFFF0000, segment length 64KB, pointing to the last 16 bytes of the last 64K. == THE BIOS stores a jump instruction that can jump up to 64KB.

>>> hex(64*1024-16)
'0xfff0'
Copy the code

The BIOS program uses 32-bit large mode, sets the segment length to 4G, copies 64KB BOIS code and data to 64KB at the 1M end of the low end of memory, and then jumps to this place to let the CPU work in real address mode.In addition to the memory and ROM BIOS, CMOS (64/128 B) with very little storage capacity is used to store the computer’s real-time clock information and system hardware configuration information. Typically housed in a block with a real-time clock chip, the ADDRESS space of CMOS memory is outside the base memory space and needs to be accessed using I/O instructions.

Controller and control card

The 80X86 uses two cascaded 8259A programmable interrupt control chips to form an interrupt controller, which is used to realize the interrupt control data access mode of I/O devices.

The ROM BIOS initializes two 8259A chips, allocates interrupt priority of level 15, and establishes an interrupt direction table at the beginning of memory 0x000~0xFFF (4KB).The INTERRUPT request number is set to the corresponding interrupt vector number in the BIOS. The Linux operating system resets the relationship between the interrupt request number and the interrupt vector number.The 8237 chip is mainly responsible for DMA function.

The 8253/8254 is a programmable timing/counter chip.

A processor on the keyboard called the keyboard encoder (8048) collects information about the status of the pressed and released keys, generating on and off scan codes.

Serial communication refers to the transmission of a bit data stream one bit at a time over a line. There are asynchronous and synchronous. Asynchronous serial communication is transmitted in a single character as a unit of communication or a frame, while synchronous serial communication is transmitted in units of many characters or bytes.Universal asynchronous receiver/transmitter control chip UART composed of serial controller to deal with the serial data receiving and receiving work.

Display control

  1. MDA Display Standard (Monochrome display adapter)

Screen display size: 80 columns x25 rows, each character with one attribute byte, one screen (one frame) 4KB. The even address byte stores character codes and the odd address byte stores display attributes. 0xb0000~0xb2000 (8KB)

Character byte position = 0xB0000 +video_num_columns*2*y + x*2;Copy the code

CGA display standard

Color graphics adapter CGA supports 7 color and graphics display modes. With 16KB video memory (0xB8000 ~ 0xBC000), even address byte storage character code, odd address byte storage character display attributes. To read and write data from a hard disk, you must use a disk controller, a logical interface circuit between the CPU and the drive. Receives CPU commands and sends seek, read/write, and control signals to the drive.

For disk controller programming, is to set the contents of the registers.