This article is based on cXUAN’s own public number: Bus design of computer composition principle
Public number a lot of hardcore articles, kneel for attention ~ ~ ~
Let’s get started.
As we know, a computer is composed of five parts: arithmetic unit, memory unit, controller, input device and output device. This concept is abstract. To put it simply, CPU contains arithmetic unit and controller, memory refers to memory, and input and output devices refer to keyboard and display respectively. Computer components need to work together to complete information processing, so how to communicate between these components? It relies on the system bus, which is the focus of this article.
Know the bus
A bus is a path that connects two computers or more functional units together and allows them to exchange data with each other. The bus can also connect computers and peripheral devices together. Bus is a very important part of computer system. Here are a few concepts to know.
- Bus width: generally defined by the number of parallel data paths bus width, the general bus width has 8 bits, 16 bits, 32 bits, 64 bits, we are now the most commonly used is the 64-bit bus, a 64-bit wide bus can transmit 64 bits of information at a time, that is, 8 bytes.
- Bandwidth: Bandwidth is a measure of the speed at which data is transferred across the bus. The bandwidth of the bus can be increased by increasing the number of parallel paths while keeping the data transmission rate constant.
- Delay: Delay is the time interval between the sending of a data transfer request and the actual data transfer.
Classification of the bus
The following we mainly introduce two kinds of bus, one is the on-chip bus, one is the system bus, the on-chip bus generally refers to the CPU chip inside, between registers and registers, between registers and arithmetic unit ALU connection.
The system bus mainly refers to the information transmission medium of CPU and memory, memory and IO devices, CPU and IO devices and other major components. The system bus can be divided into the following three categories according to the different transmission information.
- Address line
- cable
- The line of control
Let’s look at these three buses in detail
The address bus
The address bus is used to transmit the address of source data or destination data in the main memory unit.
The CPU uses the address bus to specify the location of a storage unit. The CPU can address as many storage units as the address bus can carry.
In the figure above, information is exchanged between CPU and memory through 10 address buses. Each line can transfer 0 or 1 data, so the data transferred between CPU and memory at one time is 2 ^ 10.
So, if the CPU has N address buses, we can say that the width of the address bus is N. So the CPU can look for 2 to the N units of memory.
The data bus
As the name implies, the data line is the number of bits of data transmitted at one time, and the number of bits of data bus is the width of data bus.
Data transfer between CPU and memory or other components is accomplished by data bus. The width of the data bus determines the speed of data transfer between the CPU and the outside world. The 8-data bus can transfer one 8-bit binary data (that is, one byte) at a time. 16 root data bus can transfer two bytes at a time, 32 root data bus can transfer four bytes at a time…
Control bus
Control bus is a transmission line that sends control signals on the bus. Common control signals include: clock (synchronous operation), reset (initialization operation), interrupt request/response, memory read and write, IO read and write, etc.
Control between the CPU and other components is accomplished through the control bus. The number of control buses means the number of controls the CPU provides to external devices. Therefore, the width of the control bus determines the ABILITY of the CPU to control external components.
An algorithm-based connection
In the early days of the Internet, most buses used decentralized connections (there was also a bus connection, described below), as shown in the figure below
As you can see from the graph, the CPU is the core of this decentralized connection. This connection can cause problems. When your CPU is busy with computation, there is an EXCHANGE of INFORMATION between IO and memory, and your CPU, the CPU, has to stop. The CPU efficiency is seriously affected.
You know, when you’re writing an article, your partner asks you: Why are you ignoring me today? So you need to get away from work and talk to her; After five minutes of dealing with her emotions, you can’t help but respond to a reader’s long question, so you can stop writing and help her solve the problem. Can you write effectively? The same is true for cpus.
Of course, you can also choose to go into focus mode and not reply, depending on the priority of the task, the CPU is the same.
Bus design
Memory – based connection
Later, to improve the situation, a memory-centric structure emerged, as shown below
It can be seen that this connection mode takes memory as the core, and the main functions of the components involved in the figure are as follows
- Input devices, such as keyboards and mice, convert commonly used information into data that machines can recognize
- Memory is used to store instructions and data
- An arithmetic unit is used to perform arithmetic and logical operations and store the results temporarily in the unit
- The controller is used to complete the input, operation and processing of command and control procedures and data
- The conversion process of the output device is the inverse process of the input device, that is, the result of the operation is converted into a familiar form
Because of the relationship between the arithmetic unit and the controller in the circuit structure is very close, so usually the arithmetic unit and the controller collectively referred to as CPU, the input/output equipment collectively referred to as IO equipment, memory is memory.
So modern computers are usually made up of CPU + memory + input/output devices.
After using this connection mode, the information exchange between IO and main memory can not go through the arithmetic unit, and with the development and maturity of interrupt and DMA technology, the CPU efficiency has been greatly improved.
However, this approach still does not solve the flexibility of the connection between the IO device and the host, because when we want to add an IO device, this connection method can not be handled, hence the bus connection method.
CPU – based dual-bus connection
The bus uses the connection mode shared by various I/O components. The bus is actually composed of many transmission lines, each of which can transmit binary data bit by bit. For example, 16 transmission lines can transmit 16-bit binary code at the same time.
The following is a CPU-centric dual-bus architecture
The connection shown above is a bus connection that connects components to a common set of transmission lines. The concept of dual buses can be seen from the figure. One set of buses connects the CPU and memory, called the storage bus. Another set of channels used to establish information exchange between the CPU and various I/O devices is called the IO bus.
There are also problems with this connection. When multiple components are connected to the bus, if two or more components send messages at the same time, signals will clash and the transmission will be invalid. So, only one part is allowed to send messages at a time, but more than one part can receive messages.
Single bus structure design
If the CPU, main memory, and IO devices are all attached to a set of buses through the IO interface, a single-bus connection is formed.
Here’s a question. What do you think is the biggest difference between a single-bus connection and a cpu-based dual-bus connection?
In the cpu-based dual-bus connection mode, the CPU needs to participate in the interaction between THE CPU and IO bus and the interaction between the CPU and memory. Therefore, the CPU is doing work all the time, which is also the disadvantage of the CPU, and other people will be tired to death.
Single-bus connection: The CPU, memory, and I/O are all connected to the same bus, so the interaction between memory and I/O does not require the CPU. This is the biggest change. This connection is also problematic because there is only one set of buses, and when the components need to exchange information, there will be conflicts. Therefore, in this design, the bus occupancy priority needs to be set so that each component occupies the bus in order of priority. This is the real reason why locks are used in programming languages as thread safety.
Another problem is that the CPU does not interact directly with memory, which greatly affects productivity.
Memory – centered dual – bus architecture
Another connection is a memory-centered dual bus structure, which is designed as follows
This bus design structure is very comfortable. On the basis of the single-bus structure, a storage bus is added between the CPU and memory. When the I/O uses the system bus frequently, the CPU and memory can interact with each other through the storage bus. This greatly accelerates the system working efficiency and reduces the bus overhead. The memory and I/O interaction does not need to go through the CPU.
I have uploaded six PDFS by myself, and the spread has exceeded 10W + on the Internet. After searching the public account of “Programmer Cxuan” on wechat, I reply to CXuan on the background and get all PDFS. These PDFS are as follows
Six PDF links
