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What is the I2C

The I2C bus was designed by Philips in the early 1980s to allow easy communication between components located on the same circuit board. It greatly simplified the circuit design, and I2C was used in many places in early TV sets. Philips Semiconductor moved to NXP in 2006. The I2C name is translated as Inter IC. The bus is sometimes called the IIC or I²C bus. Basic features summarized by I2C:

  • The circuit is simple, only need two lines, clock line SCL and data line SDA
  • I2C is a bus structure, and the master device addresses the slave device
  • Devices on the I2C bus can work in one master, multi-slave mode or multi-master, multi-slave mode. In multi-master, multi-slave mode, arbitration and conflict detection mechanisms must be provided.
  • The I2C master device provides the clock and the SDA can transmit data in both directions
  • The transmission rate of the I2C standard can reach 100Kbit/s, 400Kbit/s in fast mode, and 3.4Mbit/s in high-speed mode. The most commonly used transmission rate is <=100Kbit/s.

I2C hardware circuit

The hardware connection circuit of the I2C master-slave device is as follows:I2C hardware circuit features:

  • Devices connected to the I2C bus must be connected in open leakage or open collector mode to achieve line and.
  • SCL and SDA must be connected with a pull resistor, which is between 4.7K and 10K in size.
  • The number of devices connected to the bus is limited by the 400pF capacitance.

Three points need to be noted here: open leakage or open collector, pull-up resistance, line and, are discussed below. What needs to be realized is that I am not graduated from electronic major. If there is something wrong, we welcome your criticism and correction.

Open drain/collector

The above mentioned chip SDA and SCL must be connected to the I2C bus in the way of open leakage or open collector. The following will analyze why this method must be used.

First of all, what is open drain/collector? The following is an example of open collector of triode. The principle of open drain of MOS tube is similar.The figure above is the open-collector connection mode of triode. The characteristics of this connection mode are as follows:

  • The input end is “1”, that is, the high level, the triode is on, the triode C pole and E pole are on, and the output is “0”.
  • The input end is “0”, that is, low level, triode cutoff, triode output “1”.
  • Input and output are out of phase.
  • If the output is not connected to the pull resistor, the output is “high configuration” when the input is “0”.
  • The input terminal can only output “0”, but not “1”. If you want to output “1”, you need to connect the external pull resistor.
  • You can implement the “line and” function, which is described in the next section.
  • Electrical compatibility is good, pull-up resistance connected to different voltages can be connected to different systems, 3.3V access to 3.3V system, 5V access to 5V system.

The above is the open-collector hardware circuit of the triode, but there is a problem that the input and output are inverting, and additional circuits are needed to “invert” it again to make the input and output consistent.

In the circuit above, an inverting triode, namely triode 2, is added. The following are its input and output characteristics:

  • The input end is “1”, that is, the high level, the transistor 1 is on, the transistor 2 is off, the output end is “open collector”, due to the effect of pull-up resistance, the output is “1”.
  • The input end is “0”, that is, low level, transistor 1 cut-off, transistor 2 conduction, then the output end is “0”.

You can see that the phase of the input and output are the same. Ok, the above is the triode open collector circuit principle, then, why connected to the I2C bus equipment, must be open leakage or open collector connection? The fundamental reason is that this circuit can achieve the function of “wire and wire”.

Line with

As the I2C is a bus communication protocol, multiple devices can be mounted on the two signal cables of the I2C. The principle of equipment communication is to change the level of SDA regularly according to the clock on SCL to meet the requirements of data communication. Since there are multiple devices connected to the bus, it is inevitable that several devices will try to change the level on the signal line at the same time, so there will be conflicts. Therefore, if communication is to be normal, conflict must be avoided. A simple conflict prevention mechanism is as follows: before sending data, the device needs to conduct conflict detection based on checking the level state of SDA: As long as the SDA is detected to be low, the bus is occupied. To avoid collisions, the current device must wait some time to check the LEVEL state of the SDA again. If the bus becomes “idle” (that is, SDA is high), the device can communicate.

Here is a key point: how to ensure that multiple devices connected to the I2C bus, as long as there is a deviceTake upNo other device can make the bus intofree? The open collector structure mentioned above can achieve this requirement.As shown in the figure above, the output value of SDA for each device is not exactly the same, but as long as one of them is “0”, the result is “0”, here it isLine with, which can ensure that the signal on the SDA line is either stable at “0” (at least one device output is 0) or stable at “1” (all devices output is 1). Using “line and”, the device on I2C bus, can easily detect the working state of the bus, so as to achieve conflict detection and normal communication timing.

I2C sequence

The above mainly introduces the basic hardware principle of I2C bus. However, to complete the final communication between devices, the interaction of different signals must be completed strictly in accordance with a certain time sequence, which is the hardware protocol of I2C communication.

Edge control signal

The communication between I2C devices is initiated by the master device. If the master device wants to write data to the slave device, the master device puts the data to the SDA and waits for the data to stabilize. After that, the master device sends a rising edge notification to SCL to read the data from the slave device. During the high level of SCL, the data of SDA should be stable. If it is the master device that wants to read the data from the slave device, the master device sends a falling edge to the SCL to inform the slave device to put the data on the SDA. The master device reads the data on the SDA during the SCL high level. During the reading, the data on the SDA must be stable.

To sum up:

  • Write: The master device puts data on the SDA and, when the data is stable, sends an edge signal (rising edge) to inform the device to read the data on the SDA.
  • Read: The master sends an edge signal (falling edge) telling the slave to send data. After the edge signal is detected, the slave changes the data. The master reads the data during a high clock level.

Data validity requirements

  • When I2C conducts data transmission, the DATA on SDA must be stable when SCL is at high current level.
  • Data on SDA is allowed to change only when SCL is low.

Start/stop signal

The start and stop signals of I2C are as follows:

  • Both start and end signals are initiated by the master device.
  • After the start signal, the bus is in the occupied state, and after the end of the signal, the bus returns to the idle state.

The data transfer

The general rules of I2C data transmission are as follows:

  • Each byte sent to the SDA line must be 8 bits, and there is no limit to the number of bytes that can be sent per transfer.
  • The highest bit of data (MSB) is transmitted first. Each byte must be followed by a response bit, so there are 9 bits in a frame.
  • If the slave machine cannot receive or send the next complete byte of data until some other function (such as an internal interrupt service routine) is completed, the clock line SCL can be kept low, forcing the host into a wait state, and data transmission continues when the slave machine is ready to receive the next byte of data and releases the clock line SCL.

After receiving the data, the data receiver sends the data to the sender if it needs to continue receiving the dataThe replySignal; If the data receiving end does not receive data any more, it needs to send dataNot replyThe signal.

Read/write timing

Equipment addressing

When the I2C commences communication, the host initiates the bus addressing by sending a byte of the addressing address after initiating the start signal.

  • R/W bit: indicates the direction of data transmission. 0 indicates that the host writes data to the slave machine, and 1 indicates that the host reads data from the slave machine.
  • Device addresses are classified into programmable and non-programmable devices. Some device addresses are fixed and unchangeable, while others can be set by chip pins. Addressable devices can be easily connected to multiple identical devices on an I2C bus, and then distinguished by address.

I2C write sequence

The following figure shows the complete sequence diagram of the host writing a byte to the slave machine.

  • After starting the signal, the host sends the addressing byte, where bit 0 indicates that the host is writing data to the slave machine.
  • After receiving each data, the slave machine needs to send an ACK signal to indicate that the data has been successfully received.
  • After sending data, the host sends a stop signal.

The I2C read sequence

The following figure shows the complete sequence diagram of data read by the master machine. The following points need to be noted:

  • After starting the signal, the host sends the addressing byte, where the first bit, 1, indicates that the host reads the data from the slave machine.
  • After receiving each data, the host sends an ACK signal to indicate that the data has been received successfully.
  • After receiving the last byte of data, the host sends “NACK” to indicate the completion of receiving. After that, the slave machine gives up the control of SDA, the host sends a stop signal, and the data receiving process ends.