ARM assembly learning notes a

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Overview of ARM instruction

1. Features of ARM instruction set

1.1 Basic format of ARM instruction machine coding

1.2ARM assembly language instruction format

(opcoed) {(cond)} {s} (Rd), (Rn) {(operate2)}

Opcoed: opcodes, such as B(jump instruction),STR;

Cond: optional condition code, execution conditions, such as NE,EQ(equal);

S: If there is S suffix, the condition code in CPSR(status register) will be updated according to the calculation results;

Rd: target register;

Rn: register in which the first operand is stored;

Operate2: the second operand;

Such as:

/* Assume that R2 is equal to R3SUBS R1,R2,R3 ; R1 = R2 - R3 BEQ Lable ; Jump to Lable label to execute instruction/* Since SUBS has an S suffix, the CPSR register will be updated by the result obtained by this instruction. Since the content in the R1 register is 0, it can be determined that R2 is equal to R3, and the flag bit Z in the CPSR register is set to 1. B is the jump instruction because BEQ contains its condition code. Since position 1 has been marked by the previous instruction, the jump instruction here will be executed. * /
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Second, ARM addressing mode

1. Address immediately

Meaning: Operands are contained in the instruction’s 32-bit machine code; Such as:

ADD R0, R0, #5; R0 = R0 +5
AND R1, R2, #0x01; R1 = R2 AND0x01

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Note: the immediate number is 12 bits, so 0x2345 cannot be placed as an immediate number in an ARM instruction and can only be placed in operand 2.

Q: The operand 2 and the data in the register must be converted to 32-bit data when the ARM CPU LOGICAL operation unit computes. How can the 12-bit immediate data be converted to 32-bit immediate data on ARM hardware?

Solution: the 12-bit code contains an 8-bit constant and a 4-bit cyclic right shift value, which is doubled by the 8-bit constant cyclic right shift 4-bit value to get the last 32-bit immediate number.

For example, MOV R0,#0x0000F200; R0 = 0x0000F200

Machine code: E3A00CF2 Machine instruction format can be known from the above, E(1110) is the conditional code, its postfix helper is AL, the flag bit is unconditional, and the definition is also unconditional. That is, there is no condition to restrict whether the MOV instruction can be executed or it can be written as MOVAL R0,0x0000F200. For the same reason, 3A is the machine code of the MOV instruction, which will not be described here. If you do not understand, please refer to the previous notes for relevant analysis.

4-bit circular right shift value: C(decimal 12)

8-bit constant: 0xF2

Method 12 * 2=24 cyclic right shift gives a 32 bit value

0000 0000 0000 0000 0000 1111 0010

0000 0000 0000 0000 1111 0010 0000 0000

Note: Not all 32-bit immediate numbers can be encoded this way! You need to make a legal judgment before using immediate numbers. This is very unfriendly to programming, thankfully the compiler system provides pseudo instruction LDR. LDR R1 = 0 x87654321. Even if R1 = 0x87654321

2. Register addressing

Operands are stored in registers.

Basic mode:

ADD R0, R1, R2; R0 is R1 plus R2 because of the operands2Account for the12A,12Bits to describe registers R0 through R15 are perfectly sufficient,; In fact, you can describe registers R0 through R15 with four bits so you can do something else with the other bits.Copy the code

Shift operation of the second operand register:

ADD R3,R2,R1,LSR #2; R3 = R2 + R1/4
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3. Register indirect addressing

Meaning: The value of the register is used as a memory pointer, and the load/store instruction of the data transfer class uses register indirect addressing mode.

Such as:

LDR R0,[R1] ; That is, the value of R1 is the address of the memory unit and the contents of the address are put into R0. Here R1 can be understood as a pointer in C languageCopy the code

4. Base address plus offset address

• Indexed before

Such as:

LDR R0,[R1,#4]; At this point, R1 is used as the base address to add a cell to the higher address; Get the contents and put them in R0Copy the code

• Automatic indexing

Such as:

LDR R0,[R1,#4]! ; At this point, R1 acts as the base address and adds a cell to the higher address to get its contents into R0. ; And make an update to the base address register i.e. R1 = R1 +4
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• After the index

Such as:

LDR R0,[R1],#4; That is, the value of R1 is the address of the memory unit and the contents of the address are put into R0. And make an update to the base address register i.e. R1 = R1 +4
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• Register offset address

Such as:

LDR R0,[R1,R2] ; R1 is the base address and R2 is the offset address. Get the contents of R1+R2's address as an address and place it in R0. LDR R0,[R1,R2,LSL,#2]; The address is R1+R2 *4, put the contents of its address into R0.Copy the code

5. Multi-register and block copy addressing

Meaning: an instruction to complete the transmission of multi-word data or data blocks;

Basic instruction: LDM/STM

Base address register change mode:

IA: The IP address increases after the operation.

IB: The IP address is added before the operation is complete.

DA: the address is decrement after the operation.

DB: indicates that the address is decrement first and then the operation is complete.

Multi-register syntax representation:

Multiple registers are included with “{}”, continuous registers are separated by “-“, and non registers are separated by “,” for example:

LDMIA R0,{R1-R4,R6} ; R1 = [R0],R2 = [R0 +4],... ,R6 = [R0 +16]; At this point, the value of R0 is not updated LDMIA R0! ,{R1-R4,R6} ; The value of R0 is going to be updatedCopy the code

Stack addressing

Meaning: batch data transfer between data stacks and register groups in storage space;

Basic instruction: LDM/STM;

FD/ED: full decrement/empty decrement (full indicates whether there is data pressed into the position indicated by the sp pointer, empty indicates the opposite)

FA/EA: full increment/empty increment (subtraction is the way the stack grows, i.e. the address of the stack grows from the high address to the low address)

Such as:

STMFD SP! {R0-R7,LR} ; Push LDMFD SP! {R0-R7,LR} ; Pop up the stackCopy the code

7. Relative addressing

Meaning: the program counter PC as a base address register, the address label field in the instruction as an offset address, jump instruction using relative addressing mode.

The end:

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