ARM Cortex-M (1) -4 line Protocol Standard (JTAG)

Hello everyone, I am a ruffian balance, is a serious technical ruffian. Ruffian balance to you today is embedded debugging interface standard JTAG.

After the end of “ARM Cortex-M file those things” series of articles, Riffraff balance rest for a short period of time, but the heart of the lecture completely can not stop ah, so can not help but open a new series of articles, called “ARM Cortex-M debugging those things”, this is the first article in this series, In embedded development, we inevitably need to simulate and debug code, especially when the application engineering function logic is complicated to a certain extent, it is inevitable that some logic bugs will be introduced in writing code. Sometimes, only code review can not eliminate all bugs. So online debugging is the most effective and straightforward way to eliminate bugs, and today we’re going to talk about the basics of debugging, namely interface standards. The ARM kernel natively supports two common interface standards in the industry, namely JTAG and SWD. In this lesson, Ruffian balance first give you a detailed talk about JTAG interface.

JTAG interface standard

JTAG stands for “Joint Test Action Group”, which is both a standard and an organization. It was established in 1985 by several major electronics manufacturers (IBM, AT&T, TI, Philips, etc.). The purpose of this organization was to initiate the development of a PCB and chip testing standard. The JTAG standard was approved by IEEE in 1990 as IEEE1149.1 Test Access Port and boundary scan architecture standard. JTAG standard defines the hardware and software needed for boundary scan, which is mainly used in boundary scan test of circuit and online system programming of programmable chip.

1.1 IEEE 1149.1 Standard

Working group on the IEEE 1149.1 grouper.ieee.org/groups/1149… The original manual 1149.1 1990 standards.ieee.org/findstds/st… The latest edition of the manual 1149.1 2013 standards.ieee.org/findstds/st…

1.2 JTAG Interface Signals

The JTAG interface, commonly known as Test Access Port (TAP), uses the following signals to implement boundary scanning operations:

• TCK (Test clock) : Synchronizes the clock signal of the internal state machine operation.
• TMS (Test mode selection) : The mode signal that controls the internal state machine transition (TCK rising edge sampling).
• TDI (Test data input) : data moved into device test or programming logic (TCK rising edge sampling).
• TDO (Test data output) : Data removed from device test or programming logic (TCK falling edge sampling).

In addition to the above signal lines, there is an optional signal:

• TRST (Test reset) : Resets the reset signal of the TAP controller’s state machine.

1.3 Internal structure of JTAG System

The most basic internal unit of THE JTAG system is the Boundary Scan unit (the value obtained by the Scan is stored in the Boundary Scan Register (BSR)). Each Boundary Scan unit is located on the Boundary of the target device, so JTAG test is often called Boundary Scan. All signals between the core logic of the target device and the pins are intercepted by a series of boundary scanning units. During normal operation, these boundary scan units are not visible. However, in test mode these units can be used to set/read values of target device pins or core logic.

In addition to the above BSR, the JTAG system requires the following three registers:

• Instruction register: Stores the current instruction, the contents of which are used by the TAP controller to determine how to process the received signal.
• BYPASS register: unit register that transfers information from TDI to TDO.
• IDCODES: Contain device identification codes and version numbers that allow devices to be associated with their Boundary Scan Description Language (BSDL) files.

The most core of the JTAG system is the TAP controller, which is designed to interact with the internal registers of the JTAG system. The TAP controller is a synchronous state machine converted by TMS signal control and controls the behavior of the JTAG system.



As shown in the figure above, the TAP controller’s internal state machine has a total of 16 states. For the specific meanings of each state, refer to IEEE1149.1 manual. The basic function of TAP controller is to generate clock and control signals required for the normal operation of BSR and instruction register. The main functions are as follows:

• Provides a signal to load an instruction into an instruction register.
• Provides signals to move input data from the TDI pin to the internal register and output data from the internal register to the TDO pin.
• Perform functions such as capturing, shifting, and updating data.

The instruction register is used to store the instructions that need to be interpreted and executed. IEEE 1149.1 standard specifies the instructions that a JTAG compatible device must have:

• BYPASS: Uses a single cell BYPASS register to transmit data and shorten unnecessary scanning links in the JTAG chain.
• EXTEST: drives a known value (with BSR) to the chip pin.
• SAMPLE/PRELOAD: Loads the captured chip pin values into the BSR.

In addition to the required instructions, the IEEE 1149.1 standard specifies the following optional instructions:

• IDCODE: Remove the data from the IDCODES register.
• INTEST: drives a known value (with BSR) to the core logic of the chip.
• RUNBIST: When the TAP enters the idle state of the test run, the chip checks itself.

1.4 JTAG debugging tool Pinout

The debugging programming tools that usually support JTAG interface actually only use the four-wire TAP communication protocol of JTAG technology, and in addition to the standard TAP signal line, sometimes other auxiliary signal lines are added to form a complete PINOUT. For ARM JTAG debugging tools, there are two relatively common Pinout standards. ARM20 JTAG header ARM14 JTAG header

In addition to the standard TAP signal cables, the meanings of other auxiliary signal cables in the preceding two ARM JTAG headers are as follows:

Note: the more the JTAG pinout see JTAG test site of www.jtagtest.com/pinouts/

Second, JTAG interface advanced

In front of the JTAG basic knowledge, ruffian balance here to introduce some more JTAG related “black technology”.

2.1 BSDL file

Nowadays, more and more chips support JTAG interface. In order to unify the specific JTAG implementation of chip manufacturers and promote the consistency of the entire electronics industry, IEEE1149.1 standard has formulated the BSDL language specification. BSDL is a standard modeling language for JTAG devices. Its syntax is a subset of VHDL, and it describes the boundary scan characteristics of JTAG devices. It is mainly used to communicate with chip manufacturers, users and test tools.

JTAG BSDL library website (BSDL /), covering the mainstream manufacturers of the mainstream…

Freescale K60_1M (K24_144QFP) for a simple analysis:

entity k60_1m is generic (PHYSICAL_PIN_MAP : string := "K24_144qfp"); Port (PTA0: in bit; . XTAL32: linkage bit); use STD_1149_1_2001.all; use STD_1149_6_2003.all; -- Description chip pins pinout attribute COMPONENT_CONFORMANCE of K60_1M: entity is "STD_1149_1_2001"; attribute PIN_MAP of k60_1m: entity is PHYSICAL_PIN_MAP; constant K24_144qfp :PIN_MAP_STRING := "PTA0: 50," & ... "XTAL32: 40" ; -- Attribute TAP_SCAN_OUT of PTA2: signal is true; Attribute TAP_SCAN_CLOCK of PTA0: signal is (2.00e+07,BOTH); attribute TAP_SCAN_MODE of PTA3 : signal is true; attribute TAP_SCAN_IN of PTA1 : signal is true; Attribute INSTRUCTION_LENGTH of K60_1M: entity is 4; attribute INSTRUCTION_OPCODE of k60_1m: entity is "BYPASS (1111)," & "CLAMP (1100)," & "EXTEST (0100)," & "HIGHZ (1001)," & "IDCODE (0000)," & "PRELOAD (0010),"  & "SAMPLE (0011)," & "ENABLE_CENSOR_CTRL (0111)," & "ENABLE_TEST_CTRL (0110)," & "EZPORT (1101)," & "JTAGDP_ABORT (1000)," & "JTAGDP_APACC (1011)," & "JTAGDP_DPACC (1010)," & "JTAGDP_IDCODE (1110)"; attribute INSTRUCTION_CAPTURE of k60_1m: entity is "xx01"; attribute INSTRUCTION_PRIVATE of k60_1m: entity is "ENABLE_CENSOR_CTRL," & "ENABLE_TEST_CTRL," & "EZPORT," & "JTAGDP_ABORT," & "JTAGDP_APACC," & "JTAGDP_DPACC," & "JTAGDP_IDCODE"; -- Attribute IDCODE_REGISTER of K60_1m: entity is "0000" & -- Version "1011001100011010" & -- Part Number "00000001110" & -- Manufacturer Identity "1"; -- IEEE 1149.1 Requirement attribute REGISTER_ACCESS of K60_1M: entity is "BYPASS (BYPASS)," & "DEVICE_ID (IDCODE)"; Attribute BOUNDARY_LENGTH of K60_1M: entity is 196; attribute BOUNDARY_REGISTER of k60_1m: entity is -- num cell port/* function safe [ccell dis rslt] " 0 (BC_2, *, control, 1) ," & " 1 (BC_8, PTE0, bidir, X, 0, 1, Z) ," & ... " 194 (BC_2, *, control, 1) ," & " 195 (BC_8, PTD15, bidir, X, 194, 1, Z) "; end k60_1m;Copy the code

2.2 JTAG Daisy chain

When you have multiple JTAG devices in your system, JTAG supports the following Daisy chain connection (especially widely used in FPGA) to solve the problem that JTAG ports occupy too much PCB:

As can be seen from the figure above, TMS and TCK are a master-slave parallel structure (when there are too many devices in TMS, THE TCK circuit needs to add buffer (such as 74LVC245) to increase the driving capacity). TDI and TDO are a master-slave series structure. This Daisy chain mode enables PCB to access all JTAG devices with only one JTAG interface.

At this point, embedded debugging interface standard JTAG ruffian balance will be introduced, applause where ~~~

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