The directory structure

1. CPU caching basics

Cache hit

Third, cache consistency

Typical use cases

5. Queue pseudo-sharing

Introductive takeaway

Basically CPU cache knowledge is a basic knowledge point into dachang, but also quite valued, this part of the knowledge to master better words, will be very extra points!

History:

In the early decades of computing, main memory was incredibly slow and expensive, but cpus weren’t particularly fast either. Starting in the 1980s, the gap widened rapidly. Microprocessor clock speeds have skyrocketed, but memory access times have improved far less dramatically. As this gap widened, it became increasingly clear that a new type of fast memory was needed to bridge it.

CPU Caching Basics (part 1)

Today I’m going to share cache consistency and cache hits

Cache consistency

Part from Wikipedia:

In order to maintain data consistency with lower-level storage (such as memory), updates must be propagated in due time. This propagation is done by writing back. There are two Write back policies: Write Back and Write Through.

Based on the write back strategy and the missed allocation strategy mentioned above, see the following table

From the figure above, we know:

Write back: If the cache hits, the memory does not need to be updated to reduce memory write operations. Usually, the allocation policy is allocation

  • How do I flag that the cache was updated when it was loaded by another CPU? Each Cache line provides a dirty bit to indicate whether an update has occurred since it was loaded. (The CPU is loaded chunk by chunk, not byte by byte, as mentioned earlier)

Writing:

  • Write through means that whenever the cache receives a write instruction, it writes the data directly back to memory. If this data address is also in the cache, the cache must be updated at the same time. Since this design causes a lot of write operations, it is necessary to set up a buffer to reduce hardware collisions. This buffer is called a Write buffer and is usually no larger than four cache blocks. However, write buffers can also be used for write-back caches for the same purpose.

  • Write through is easier to implement than write back, and it is easier to maintain data consistency.

  • Usually allocation strategies are non-allocation

For a two-level cache system, level 1 cache may use write pass to simplify implementation, while level 2 cache uses write back to ensure data consistency

The msci protocol:

Here is a webpage this address is too 6x, referred to a lot of information, or animation… www.scss.tcd.ie/Jeremy.Jone…

It is recommended to play the GIF of the website above first to understand the read and write data of each CPU’s cache and main memory.

Here’s a quick explanation: our main store has a value of x=0, and the processor has two CPU0’s and cpu1’s

  • Cpu0 reads the value of x in cpu0’s cache. If cpu0 can’t find the value, there is an address bus, which is to route the CPU and main memory, search for the CPU and main memory at the same time, compare versions, go to main memory to get x, get the value of X, and assign the value to CPU0’s cache through the data bus

  • Write to x+1, obtain the value of x=0 from cpu0, and add 1.

  • If cpu1 does not find the value of x, it searches for the value of X in CPU and main memory according to the address bus, compares the version (if the version is the same, the main memory value will be deleted first), and finds the value of X in CPU 0. Cpu0 updates the value of X in CPU 1’s cache through the data bus, and then updates the value of x in main memory

  • For x+1, cpu1 directly obtains CPU 1’s x=1 and increses it by 1. (Main memory is updated and CPU 0’s cache is not updated, but other cpus are notified by RFO

Other situations you can try yourself.

Notification Agreement:

Snoopy agreement. This protocol is more of a data notification bus technology. CPU caches use this protocol to identify data states in other caches. If data is shared, the status of shared data can be notified to other CPU caches through a broadcast mechanism. This protocol requires that each CPU Cache be able to “snoop” on notifications of data events and react accordingly.

MESI protocol status:

A) Modified B) Exclusive C) Shared D) Invalid

Follow the animation again, in fact, is not very complicated.

This is actually useful to understand the volatile keyword in Java!

The following document is a typical use case!

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