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The modern CENTRAL Processing Unit (CPU) is a large scale integrated circuit. We know that the computer world is made up of zeros and ones. That’s because the transistors that make up the CPU are only on and off. There are billions of transistors inside a CPU, and more and more. The CPU is like a large factory storing switches, each transistor is a switch, 0 means off, 1 means on, the more transistors, the more switches. The more switches you have to work with, the faster you can work on the same problem.
Traditionally, CPU consists of two main components: controller and arithmetic unit. With the continuous development of IC, some new functional components are continuously integrated, such as floating point processor, Cache, etc., which greatly improve the CPU performance index. In summary, CPU can be logically divided into three modules:
- The control unit
- The controller is the command center of the entire computer system. Under the command and control of the controller, the components such as arithmetic unit, memory and input/output devices work together to form a complete general-purpose computer. It usually contains program counter PC, Instruction Register IR(Instruction Register), Instruction Decoder ID(Instruction Decoder), Operation Controller OC(Operation Controller) and timing generator, etc.
- Instruction counter & instruction register
- Instruction register: Holds the address of the currently executing instruction. When the next instruction is executed, it is read from memory into the buffer register and then transmitted to the instruction register.
- Instruction counter: Used to determine the address of the next instruction, the process by which the CPU executes an instruction. The first step is to fetch an instruction and place it in an instruction register. The address of the next instruction is then calculated and fed into the program counter.
- The instruction counter stores the computed address of the next instruction and then accesses the data and places the instruction address in the instruction register. That is, one is used to store the current instruction (register) and one is used to store the address of the next instruction (counter).
- Instruction decoder
- Decode the instruction, and generate the corresponding operation control signal, so as to start the corresponding action.
- Operating controller
- Generate various operation control signals, command and control the CPU. It generates various operation control signals according to the command opcodes and timing signals, so as to correctly establish the data path, so as to complete the control of command fetching and command executing.
- Sequence generator
- A sort of “wake time” in the CPU that allows a computer to work accurately, quickly and methodically. Once activated, the machine CPU began to take instructions and perform the operations controller using timing pulse sequence and different pulse interval, organized and with rhythm, the command of the machine movement, provisions in the pulse arrival do, in the pulse arrival and what to do, the computer parts provide the time needed for the job.
- The operation unit
- The part used to realize data processing and other functions, which accepts the command of the controller and is responsible for completing the processing tasks of operational data (performing arithmetic operations, including basic operations such as addition, subtraction and multiplication and its additional operations and logical operations, including shift, logical test or comparison of two values), Its core part is Arithmetic Logic Unit (ALU). Its components also include: accumulator register (AC), data register (DR), program state word register (PSW) and so on.
- Arithmetic Operation Logic Unit (ALU)
- An arithmetic logic unit consisting of and and or gates whose primary function is to perform all arithmetic operations. Obviously, there must be at least one cumulative register in an arithmetic unit
- Accumulator (AC)
- When the ALU performs arithmetic or logical operations, it provides a workspace for the ALU to temporarily store the operation result information.
- Status Register (PSW)
- ALU saves the contents of various condition codes established by the results of running or testing when performing logical operations, such as carry mark, overflow mark, zero mark, negative mark and so on.
They are connected to each other by an internal bus. In simple terms, the CPU is mainly composed of a lot of arithmetic units, controllers, registers. Its internal structure is shown in the figure below:
Operation principle
Von Neumann architecture is the basis of modern computers. In this architecture, programs and data are stored uniformly, and instructions and data need to be accessed from the same storage space and transmitted through the same bus, so execution cannot overlap. According to the Von Neumann system, the operation process of CPU will take out instructions and corresponding data from memory or cache one by one. According to the provisions of the instruction opcode, the data will be calculated and processed until the program is executed. It is generally divided into the following four stages: instruction fetching stage, instruction decoding stage, instruction executing stage, and result writing back.
- Fetch instruction: THE CPU controller reads an instruction from memory and places it in an instruction register.
- Instruction decoding: Instructions in an instruction register are decoded to determine what operation the instruction should perform (that is, the opcodes in the instruction) and where the operands are (the addresses of the operands).
- Execution instructions: This stage performs calculations by connecting to various CPU parts capable of performing the required calculations. For example, when performing an addition operation, the ALU will connect to a set of inputs that provide the values to be added, and a set of outputs that contain the sum.
- Result write back: Simply write the result of the execution back to register or memory in a format.
After the instruction is executed and the result is written back, the program counter value is incremented, the whole process is repeated, and the next instruction cycle normally extracts the next sequential instruction.