Excellent PCB designers are also excellent artists. However, with the commercialization of 5G and the popularity of Internet of Things devices, circuit board routing is becoming more and more precise, signal frequency is increasing, electromagnetic interference is becoming more and more serious, and PCB designers have to face a practical problem: The PCB has begun to act as a component with resistance, capacitance and inductance, rather than as a platform for wiring, as it did 10 years ago. The problems of electromagnetic compatibility and signal integrity are becoming more and more prominent, and the requirements for PCB wiring and component layout are becoming higher and higher.

This paper first introduces the PCB manufacturing process and components packaging related knowledge, and then focuses on the author’s work summarized in the process of some PCB Layout of the basic wiring specifications and design principles. Of course, as a relatively systematic engineering problem, the experience and principles of signal integrity are not absolutely applicable to any occasions, and the actual wiring still needs specific analysis and design combined with the actual working conditions. There will be a separate article on the complexity of signal integrity.

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Basic terminology

At present, the global EDA industry pattern is mainly monopolized by Synopsys, Cadence and Mentor. Among them, Cadence’s Allegro(/əˈle ʊ ʊ/) is a high-speed PCB level wiring tool that is highly respected in the industry. Of course, in the face of expensive commercial License, you can also choose KiCad, which is free and easy to use.

Printed Circuit Board (PCB) is an acronym for Printed Circuit Board (PCB). The substrate of PCB is composed of dielectric layer (insulating material) and high purity conductor (copper foil). The common substrate of PCB is copper foil epoxy glass fiber laminate, also known as FR-4 glass fiber Board. Laminated with fiberglass cloth impregnated with epoxy resin.

  • Network: Circuit is also called network, namely circuit network;
  • Board and frame: Before placing THE PCB package, draw the border of the PCB board on the corresponding layer.
  • Flying wire: it is generated based on the same schematic network. When the network of two packages of pads is the same, flying wire will appear, indicating that the two pads can be connected by wire in PCB.
  • Pads: used to fix and connect electronic components to the PCB, each pad has a separate number for easy matching with component pins;
  • Teardrop: smooth the connection between the transition wiring and pad, improve the reliability of the connection, reduce the sharp jump in impedance during signal transmission, avoid high frequency signal due to the sudden reduction of line width caused by reflection;
  • Copper laying: used to reserve the whole copper foil area of the connection ground or power supply. A PCB can be set and draw multiple copper laying areas respectively.

wiring

  • Differential pair wiring: Differential pair is an effective high-speed signal wiring method, which can suppress common mode noise and achieve better signal integrity; Among them, equal length and equal distance are the most basic requirements of differential wiring;
  • Serpentine isometric wiring: Serpentine wiring is used to solve the arrival time difference of parallel signals caused by unequal line lengths under high-speed signals, which leads to the change of signal timing. It has no so-called filtering or anti-interference ability, so it is only suitable for the purpose of timing matching;

The makeup

  • Board: used to make full use of PCB boards, placing multiple identical or different PCB designs on one board, thus improving production efficiency;
  • V cut: also known asV-CUT, refers to the board factory in accordance with the customer’s requirements (for laterPoints plate), pre-cut the printed circuit board at a specific position using a cutting machineVV slot, because v-cut can only go straight, not curve and broken line, so regular PCB board will adopt this way; In addition, PCB wiring distance V secant distance should not be less thanThe 0.4 mmTo avoid damage;
  • Stamp hole: one is in order to facilitate the late board, in the position of the board hit some holes, because it is easy to cause burr and other problems, so only used for the irregular occasions of the board; The other is often used in the core plate, with connection characteristics of the stamp hole, the use of precise cutting for half hole;

A hole

Via Hole is a small copper plated metal Hole used for electrical connection between different copper layers. It can be divided into the following three types:

  1. hole(Through) : connect the top and bottom layer and run through the whole PCB;
  2. Blind hole(Blind) : one end is located on the PCB surface, and the other end is located on the working layer in the middle of the PCB;
  3. Buried hole(Buried) : used for the connection between the two working layers in the middle of PCB;

Note: For the sake of signal integrity, PCB design should minimize the use of holes; If it is necessary to use through holes, try to avoid using blind holes and buried holes, which not only increase the difficulty of PCB processing, but also bring a lot of electrical safety problems.

Resistance welding

Solder Mask, also known as Solder Mask, refers to the part of PCB that needs to be covered with Solder ink. The Solder layer usually uses negative output, so the shape of Solder layer is mapped to the PCB not to fill Solder ink, but to expose the copper foil.

Resistance welding bridge

The solder bridge is the solder between the patch components (the width of the solder oil is reserved between the two solder Windows, usually greater than 6mil), mainly used to prevent the solder pad from short circuit during welding.

Resistance welding open the window

Solder blocking window refers to the part of the copper-clad board that does not cover the ink, that is, the copper part that exposes the surface of the PCB.

Unit conversion

The mille is a unit of length often used in PCB design. It represents one thousandth of an inch and is usually written as mIL. The conversion is as follows:

1Mm (mm) ➜39.37Mil1Mil (Mil) ➜0.0254Mm (mm) ➜25.4μm (micron)1Inch ➜1000Mil (Mil) ➜25.4Mm (mm)Copy the code

protel

Package describes the shape and size of electronic components. Components with the same electronic parameters may have different packages. As packaging technology changes with each passing day and there is no unified standard, this paper summarizes some commonly used packaging types of electronic components.

SMT components

SMT is the abbreviation of Surface Mounting Technology. Common SMT components are 0201, 0402, 0805, 0603, 1206, 1210, 1812, 2010, and 2512.

English system (MIL) Long (mm) Width (mm) High (mm) Rated power (resistance) Maximum operating voltage (resistance) Metric system (mm)
0201 packages  0.60mm ± 0.05  0.30mm ± 0.05  0.23 毫米 ± 0.05 1/20 W 25V  0603
0402 packages  1.00 毫米 ± 0.10  0.50 毫米 ± 0.10  0.30 毫米 ± 0.10 1/16 W 50V  1005
0603 packages  1.60mm ± 0.15  0.80mm ± 0.15  0.40mm ± 0.10 1/10 W 50V  1608
0805 packages  2.00mm ± 0.20  1.25 毫米 ± 0.15  0.50 毫米 ± 0.10 1/8 W 150V  2012
1206 packages  3.20mm ± 0.20  1.60mm ± 0.15  0.55 毫米 ± 0.10 1/4 W 200V  3216
1210 packages  3.20mm ± 0.20  2.50mm ± 0.20  0.55 毫米 ± 0.10 1/3 W 200V  3225
1812 packages  4.50mm ± 0.20  3.20mm ± 0.20  0.55 毫米 ± 0.10 1/2 W 200V  4832
2010 packages  5.00mm ± 0.20  2.50mm ± 0.20  0.55 毫米 ± 0.10 3/4 W 200V  5025
2512 packages  6.40mm ± 0.20  3.20mm ± 0.20  0.55 毫米 ± 0.10 1 W 200V  6432

Chip packaging

Semiconductor chip packaging materials are mainly plastic, ceramics, glass, metal and so on, if there is no special process requirements, now commonly used is plastic packaging:

Encapsulation abbreviations Package name instructions
SIP Single in-line Package Single inline package
DIP Dual in-line Package Double in-line package
SOP Small Out-Line Package Small profile package (dual column)
QFP Quad Flat Package Square flat packaging technology
QFN Quad Flat Non-leaded Package Four side pin less flat package
COG Chip on Glass The chip is mounted into the LCD glass
CSP Chip Scale Package Chip package
PGA Pin Grid Array Package Pin grid array package
BGA Ball Grid Array Package Ball grid array package
C/PLCC Ceramic/Plastic Leaded Chip Carrier Ceramic/plastic has lead chip carrier

Wiring parameters

Currently, THE default PCB board factory adopts fr-4 board with 1.6mm thickness:

  • The outer copper thick:1oz ~ 2oz, i.e.,35um ~ 70um, the default thickness of the outer copper foil of the conventional circuit board is1 ozAt most, you can do it2 oz(Note required);
  • The inner layer copper thickness:0.5 oz., i.e.,17um, the default thickness of the copper foil line in the inner layer of the conventional circuit board is0.5 oz.;
  • Minimum line width and clearance: jia gen3.5 mil, the match4milAnd the two are approximately equal toThe 0.1 mm, the actual wiring should be greater than4milCan;
  • Minimum diameter inside and outside of hole: Minimum inner diameter of multilayer panelThe 0.2 mm, the minimum outer diameter isThe 0.4 mm, double panel minimum idThe 0.3 mm, minimum outside diameterThe 0.5 mm;

Note: for specific parameters, please refer to the documents of PCB factory, such as “PCB Process Parameters of Jialichuang”, “Manufacturing Process Requirements of Jialichuang”, and “PCB Process Capability of Jiejie”.

Wiring width

IPC stands for The Institute of Printed Circuit, an organization that provides guidelines and standards for PCB design and manufacturing:

  • Ipc-7525 Steel Mesh Design Standard
  • IPC-2221 General Standard for PCB Design
  • Ipc-sm-782 Welding Pad Graphics standard for Surface Mounting Design
  • Ipc-sm-770 Printed Board Assembly Assembly Specification (Including Design Requirements for Surface mounting and Perforated Mounting)

The following line width calculation formula is derived from “IPC-2221 General Design Standard for Printed Circuit Boards” **. It is suitable for outer current 35A, inner current 17.5a, temperature 100C°, width 400mIL:


Maximum current ( Ann ) = K x The temperature rises relative to the environment ( c ) 0.44 x ( Wiring width x The thickness of the wiring ) 0.725 , including K = The inner wiring 0.024 Or outer wiring 0.048 Maximum current (amps) = K \times Relative ambient temperature rise (c)^{0.44} \times (wiring width \times wiring thickness)^{0.725}, where K = 0.024 for inner wiring or 0.048 for outer wiring

Currently, the thickness of finished copper outer layer processed by PCB board factory is between 1oz ~ 2Oz (i.e. 35μm ~ 70μm). By default, the thickness of outer copper foil line is 1oz (at most 2OZ can be achieved), and the thickness of inner copper foil line is 0.5oz (i.e. 17μm). Based on the default wiring thickness of 35μm, the following commonly used wiring widths, maximum current and impedance can be obtained:

Wiring width Maximum passing current impedance
The 0.1 mm 0.450486 A 0.0982857 Ω
The 0.2 mm 0.744609 A 0.0491429 Ω
The 0.3 mm 0.999067 A 0.0327619 Ω
The 0.4 mm 1.23077 A 0.0245714 Ω
The 0.5 mm 1.44689 A 0.0196571 Ω
The 0.6 mm 1.65136 A 0.016381 Ω
The 0.7 mm 1.84662 A 0.0140408 Ω
The 0.8 mm 2.03433 A 0.0122857 Ω
The 0.9 mm 2.21568 A 0.0109206 Ω
The 1.0 mm 2.39156 A 0.00982857 Ω
The 1.2 mm 2.72953 A 0.00819048 Ω
The 1.5 mm 3.20884 A 0.00655238 Ω
The 2.0 mm 3.95301 A 0.00491429 Ω
The 5.0 mm 7.6813 A 0.00196571 Ω

Line spacing

Safety distance refers to the shortest space distance measured between two guiding electronic components or wires, that is, the shortest distance that can be insulated through air under the premise of ensuring stable and safe electrical performance. The table below shows the minimum safe spacing, according to IPC 2221 General Design Standard for Printed Circuit Boards.

voltage The inner conductor Outer conductor (altitude < 3050 m) Outer conductor (altitude > 3050 m) Outer conductor (permanent polymer coating) Outer conductor (conformal coating) External component pins/terminals External component pins/ends (conformal coating)
0 ~ 15 V The 0.05 mm The 0.1 mm The 0.1 mm The 0.05 mm The 0.13 mm The 0.13 mm The 0.13 mm
16 ~ 30 V The 0.05 mm The 0.1 mm The 0.1 mm The 0.05 mm The 0.13 mm The 0.25 mm The 0.13 mm
31 ~ 50V The 0.1 mm The 0.6 mm The 0.6 mm The 0.13 mm The 0.13 mm The 0.4 mm The 0.13 mm
51-100 The 0.1 mm The 0.6 mm The 1.5 mm The 0.13 mm The 0.13 mm The 0.5 mm The 0.13 mm
101 ~ 150 V The 0.2 mm The 0.6 mm The 3.2 mm The 0.4 mm The 0.4 mm The 0.8 mm The 0.4 mm
151 ~ 170 V The 0.2 mm The 1.25 mm 3, 2 mm The 0.4 mm The 0.4 mm The 0.8 mm The 0.4 mm
171 ~ 250 V The 0.2 mm The 1.25 mm The 6.4 mm The 0.4 mm The 0.4 mm The 0.8 mm The 0.4 mm
251 ~ 300 V The 0.2 mm The 1.25 mm The 12.5 mm The 0.4 mm The 0.4 mm The 0.8 mm The 0.8 mm
301 ~ 500 V The 0.25 mm The 2.5 mm The 12.5 mm The 0.8 mm The 0.8 mm The 1.5 mm The 0.8 mm

Note: most boards currently provide minimum wiring spacing of 4mil, i.e. 0.1mm.

The minimum via

The minimum inner diameter and outer diameter of multilayer boards currently available from PCB board manufacturers are 0.2mm and 0.4mm, and the minimum inner diameter and outer diameter of double panels are 0.3mm and 0.5mm.

Package size

PCB stacking and layering

Although PCBS can be designed in multiple layers, typically components can only be welded on the top or bottom layers by wave soldering (for SMT components) or reflow soldering (for discrete components) :

PCB can be divided into the following three types according to the number of copper coating layers:

  • Single-sided PCB board: only one side of the wire or copper coating;
  • Double-sided PCB board: the top and bottom layer will be wiring or copper coating;
  • Multilayer PCBIn addition to the top and bottom layers, the middle containsSignal layer,The middle layer,The power supply layer,Ground planeEach layer is insulated from each other and connected through holes;

Note: Double-sided PCBS are usually only used in low-speed designs because of their poor electromagnetic compatibility.

Each PCB layer can be connected with through hole, blind hole and buried hole respectively. In general, most board-level EDA tools and software define the following PCB functional levels:

The name of the describe
Top/bottom Copper foil layer on top and bottom of PCB board, used for signal wiring.
The inner layer Covered with copper foil, used for signal wiring and copper laying, can be set as signal layer and internal electrical layer.
Top/bottom screen printing layer A layer of characters (usually white) printed on a PCB board.
Top/bottom solder paste layer Also called positive processHelp the welding layer, used to manufacture stainless steel mesh layer for the patch pad, so as to determine the size of solder paste filling area to assist welding, the layer can be ignored without the patch;
Top/bottom resistance welding layer: The top and bottom layer of PCB cover oil layer (usually green blocking oil), its role is to prevent solder bonding plate; This layer is a negative drawing method. When there are wires or areas that do not need to be covered with solder oil, the corresponding area of the produced PCB will not be covered with solder oil. This operation is usually calledOpen the window;
Border layer This layer is used to define the shape and size of the board and frame. The board factory will produce PCB based on this layer.
Top/bottom assembly layer Simplified outline of components for assembly and maintenance, which can be exported for printing without affecting PCB board production;
Mechanical layer It is used to record the mechanical information of some PCB boards. By default, the shape defined by this layer will not be used for manufacturing during production. Some board factories will use the mechanical layer as the frame when using the source file for productionGerberThis layer is used only for identification during file productionThe process parameters,V cutting pathSuch as text information;
Document layer Similar to the mechanical layer, but this layer is only visible in EDA tools and does not export toGerberIn documents;
Fly line layer Display PCB network fly-line, not in the physical sense of the layer, just to facilitate color Settings, so some EDA tools will put it toThe layer managerTo configure;
Hole layer Similar to fly line layer, not a physical layer, used onlyhole(non-metallic hole) display and color configuration use;
multilayer Similar to the fly wire layer, the display and color configuration of the metallized holes, when the pad layer property is multi-layer, this layer will be used to connect each copper foil layer including the inner layer;
Wrong layer Similar to the fly line layer, error sign display and color configuration for DRC (Design rule verification);

Note: the signal layer is mainly placed with copper film wires and components to provide transmission channels for electrical signals; The internal power/grounding layer, also known as the internal electrical layer, is mainly used for laying power and grounding and is covered by a large copper film to improve the stability of PCB operation.

Four layers PCB reference design

Plate layer order Level 1 Layer 2 Layer 3 Layer 4
Case number one Ground plane (Signal 1 + power supply) (Signal 2 + power supply) grounding
Case number two Signal is 1 Ground plane The power supply layer Signal 2
Case number three Ground plane Signal is 1 Signal 2 The power supply layer
  • In the first case, the ideal four-layer stacking design, because the outermost layer is connected to the ground, EMI shielding, and the power supply layer and the ground can be very close, so that the internal resistance of the power supply is small; However, when the density of components is relatively high, the integrity of the ground layer cannot be guaranteed, and the signal quality of the signal layer will become poor, and the crosstalk between adjacent signal layers will be large.
  • In the second case, this method is more commonly used. This structure has better layer capacitance effect, and the inter-layer crosstalk of the whole PCB is small, so the signal layer can achieve better signal integrity. However, in this structure, because the signal layer is on the surface, the intensity of space electromagnetic radiation increases, and the EMI can be reduced by adding a shielding shell.
  • Case number three, the power supply layer and the ground layer are in the surface layer, and the signal integrity is betterSignal is 1The signal quality is best at the layers,Signal 2The level; This design has a certain shielding effect on EMI; However, because of the large loop, the density of the device directly determines the signal quality, the adjacent signal layer can not avoid interlayer interference, overall inferior to the first structure, unless there is a special requirement for power supply;

Six layers PCB reference design

Plate layer order Level 1 Layer 2 Layer 3 Layer 4 The fifth floor 6 layers
Case number one Signal is 1 Ground plane Signal 2 Signal 3 The power supply layer Signal 4
Case number two Signal is 1 Signal 2 Ground plane The power supply layer Signal 3 Signal 4
Case number three Signal is 1 Ground plane Signal 2 The power supply layer Signal 3 Signal 4
Case number four Ground plane Signal is 1 The power supply layer Ground plane Signal 2 Ground plane
  • Case number oneIs one of the common ways,Signal is 1Layer is a better wiring layer,Signal 2The level; But be carefulSignal 2 与 Signal 3Interlayer crosstalk between,Signal 4If there are no components, reduce signal lines as much as possible, and cover a layer of grounding;
  • Case number two.Signal 2 与 Signal 3Layer has the best signal integrity among themSignal 2Layer is the best wiring layer,Signal 3The level; The impedance of the power supply plane is good, and the capacitance between layers is large, which is beneficial to suppress the EMI of the whole board. But because theSignal is 1 与 Signal 2There is a large interlayer interference between the two layers, and it is far from the power supply layer and the grounding layer, and the EMI space radiation intensity is high, which may require additional shielding shell;
  • Case number threeThis situation is the optimal layout of the six-layer board,Signal is 1,Signal 2,Signal 3Are better wiring layer, and the impedance of the power plane is better, the fly in the ointment isSignal 4Too far from the ground;
  • In the fourth case, although the performance is better than the previous three, the number of wiring layers is only 2;

Signal integrity problem

Signal Integrity (SI, Signal Integrity) refers to the Signal through the Signal transmission on the PCB later still can maintain complete and accurate, when the circuit of the Signal can be in the correct sequence, conform to the requirements of the duration and the voltage amplitude of transmission, and the complete arrived at output end, which shows that the circuit has good Signal Integrity; When the signal does not respond properly, it is considered that there is a signal integrity problem, especially in high frequency and high speed circuits. Therefore, the purpose of signal integrity analysis is to ensure the correct transmission of signal timing and voltage amplitude. Common signal integrity problems in circuit design are mainly concentrated in the following aspects:

  • Transmission delay(Transmission Delay) : indicates that the signal does not reach the receiving end within a specified period of time with a certain duration and amplitude, usually due to the effect of drive overload and long wiring. In addition, the capacitance and inductance on the transmission line will also delay the signal state switch. Transmission delay is an unavoidable problem in high-speed circuit design, so a special one is introducedDelay toleranceThe concept is to ensure the normal operation of the circuit under the premise of allowing the maximum signal timing change.
  • reflection(Reflection) : refers to the echo on a transmission line. Part of the signal power passes through the transmission line from the source end to the load and part of the signal power is reflected back to the source end. In high-speed circuit design, wires can be equivalent to transmission lines rather than lumped – parameter circuits. If the impedance matches (source impedance, transmission line impedance and load impedance are equal), the reflection will not occur; Conversely, a mismatch between the load impedance and the transmission line impedance can cause the receiver to reflect the signal back to the source. Wiring geometry, improper terminations, transmission through connectors, and discontinuities in the power plane can all contribute to this problem, which can lead to severe transmissionovershoot(Overshoot) ordown(Undershoot) phenomenon, and eventually cause signal waveform deformation and timing disorder.
  • harass(Crosstalk) : Electromagnetic coupling caused by induced voltage and current between signal lines without electrical connection, which causes the signal line to act like an antenna. Among them, capacitive coupling will lead to coupling current, inductive coupling will lead to coupling voltage, which will increase with the increase of clock rate and the decrease of PCB size, all because there is alternating signal current on the signal line through the magnetic field generated, other signal lines in the magnetic field will be induced to signal voltage. The parameters of PCB working layer, the distance between signal lines, the electrical characteristics of driving and receiving end, the connection mode of signal line itself, etc.
  • Ground bounce(Ground Bounce) : To because due to the large current flowing in a circuit, and between the power and ground plane of a lot of noise, such as a large number of chip synchronous switch will be in large instantaneous current, with the power plane and chip packaging and power between the parasitic resistance, capacitance, inductance will then cause the power supply noise, causing circuit produce large voltage fluctuation on the zero potential, Then affect the normal work of other components.

Note: Signal integrity issues often go hand in hand with emc issues.

3 w / 20 h / 55 principle

  • Principle 3 w: Also known as the 3H principle, ensure that the center distance between two cables is greater than or equal toThree times the line widthTo reduce crosstalk between cables; If the distance between the center of the cables is greater than 3 times the width of the cables, keep the distance70%The electric fields between the lines do not interfere with each other; If you want to achieve98%If the electric fields between the lines do not interfere with each other, it can be used10WRules;
  • The principle of 20 h: The edge of a multilayer PCB will radiate electromagnetic interference outwards, allowingThe power planeRelative sizeGround planeIndented and spaced from one another in size20By doubling the size, the electric field can conduct only in the range of the ground layer, so as to effectively suppress the edge radiation effect. The shrinkage20HYou can70%The electric field is confined to the ground layer and shrinks inward100HYou can limit98%Electric field;
  • The principle of 55: The clock frequency reaches5MHzOr the rise time of the pulse is less than5ns, then PCB must use multi-layer board; Sometimes, for cost reasons, the double plate structure is used. In this case, it is best to use one layer of PCB as the complete ground plane layer.

PCB layout specification

  1. Power supply and signal to separate;
  2. Signal input and output should be separated;
  3. The digital part should be separated from the analog part;
  4. High frequency part and low frequency part should be separated;
  5. The strong current part should be separated from the weak current part.

Basic component layout principles

  • Under normal conditions, all components should be distributed on the same surface of the PCB. Only when the top layer of the PCB is too dense, some patch components with limited height and low calorific value should be placed on the bottom layer.
  • According to the wiring principle of “large before small, difficult before easy”, important unit circuits and core components should be laid out first, and the key signal lines should be kept the shortest.
  • The high-voltage and high-current signals are completely separated from the low-current and low-voltage signals; Analog signal separated from digital signal; High frequency signals should be separated from low frequency signals, and the isolation of high frequency components should be sufficient;
  • During the layout process, make full reference to the principle block diagram and place the main components according to the main signal flow direction;
  • The layout of the components should facilitate the flow of signals and allow the signals to flow in as consistent a direction as possible.
  • On the premise of ensuring electrical performance, components should be placed on parallel or vertical grids for neat appearance;
  • If there is a high potential difference between components or wires, the distance between them should be increased to avoid accidental short circuit caused by discharge breakdown;
  • Components with high voltage should be placed as far as possible in places not easily accessible by hand during debugging;
  • Components located at the edge of the PCB shall be at least 2 plate thickness away from the edge;
  • Insert components of the same type should be placed in the same direction, and polar components of the same type should be placed in the same direction as far as possible to facilitate later production testing;
  • Avoid contact between components of different metal packages;
  • The distance between components should meet the requirements of operating space, such as inserting and removing TF cards;
  • Components with large weight should be installed near the PCB support point to reduce the warpage degree of PCB plate force; When necessary, fixed measures should also be taken, not only rely on pin welding surface fixed;
  • Maintain a wide electrical isolation belt between high-voltage components and low-voltage components, that is, do not place components with large voltage grade differences together, which is conducive to electrical insulation and signal isolation to improve anti-interference ability;

Prevention of electromagnetic interference

  • For components with strong electromagnetic radiation, or for components that are sensitive to electromagnetic radiation, the distance between each other should be increased or a shielding cover should be added, and the direction of the components should be crossed with the adjacent copper conductor;
  • For transformer, speaker, inductor and other magnetic field components, the layout should pay attention to reduce the cutting of magnetic lines for printed wires, adjacent components magnetic field direction should be perpendicular to each other, reduce the coupling between each other;
  • Inductance devices should not be placed side by side close to avoid mutual inductance;
  • Shielding electromagnetic interference sources and ensuring that the shielding cover can be well grounded;
  • For high frequency circuits, the influence of distributed parameters between components should be considered.

Suppression of thermal interference

  • The heating element is preferentially arranged in the position conducive to heat dissipation. If necessary, heat sink and heat dissipation fan can be set separately.
  • Some components with large power consumption, large or medium power tubes, resistors and other components should be placed in places where heat dissipation is easy and separated from other components.
  • When components are placed on both sides of PCB, heating elements are generally not placed on the bottom layer;
  • Thermal elements such as resistors, capacitors and crystal oscillators should be kept away from high-temperature areas as far as possible to avoid thermal interference.
  • The thermal components should be placed in the upper air outlet as far as possible, and the high components should be placed behind the low components, and placed in the direction of the minimum wind resistance to avoid obstruction of the air channel;
  • Large area grounding copper foil is used to improve the heat dissipation efficiency of PCB.
  • Larger pads can be used for ground mounting holes to make full use of copper foil on both sides of mounting bolts and PCB for heat dissipation;

The power layout

  • More star topology, less Daisy chain layout, shorten the public circuit of power supply;
  • The input and output of the power supply should be arranged separately to avoid crosstalk problems.
  • Power management chip, backlight chip, boost chip need to be placed in the shielding shell;
  • Power cable should avoid rf area as far as possible;

High speed components and antenna layout

  • Storage chips such as DDR, SDRAM, and NAND Flash must be placed close to the CPU, and the cable length and the number of crossed wires should be minimized.
  • The screen socket should follow the direction of the CPU outlet, and the RC filter in the middle should be placed on the CPU side as far as possible.
  • The CPU of high-speed components and the socket of LCD screen should be kept away from the antenna module.
  • Do not have metal components around the RF module and antenna to avoid affecting the antenna’s frequency points, impedance and other parameters.

PCB wiring principles

  • High-speed signal wiring should be as short and straight as possible, the spacing of wiring should be large enough, and as close as possible to the edge of PCB or connector;
  • The line width of the same signal transmission line should be kept consistent, and the same line width should be kept when turning the line.
  • Important signal lines can be widened to reduce their characteristic impedance;
  • Key signal lines can be isolated by parallel ground lines.
  • Between the two adjacent layers, the line is staggered with # type wiring;
  • The width of each wire shall be symmetrical with the pad connection of each pin of the component, and the wire shall be routed from the center of the pad of the component;
  • When the wire connected to the pad is wider than the pad, the wire can not cover the pad, the wire should be led from the end of the pad;
  • Pad pins of patch components with relatively dense pin spacing need to be connected from the outside of the pad by wire, not allowed to directly connect the pads between the pins;
  • Perforation may cause impedance mutation of signal transmission line, so the number of perforation should be reduced as much as possible.
  • The pile line should be avoided on the signal transmission line. If it cannot be avoided, the length of the pile line should be less than the rise time of the signal to avoid reflection.
  • When high-speed signal wiring layer change, there should be a grounding hole nearby to provide a reflux loop, to ensure that the whole board loop small impedance;
  • Do not use the automatic wiring function of EDA tools for analog signals;
  • For sensitive nodes, shielding wires are used, that is, a group of shielding wires are added around the affected nodes, and multiple grounding holes are placed on the shielding wires;

crosstalk

  • The crosstalk caused by parallel reverse current is larger.
  • Crosstalk intensity is proportional to the length of the line, inversely proportional to the spacing, proportional to the frequency;
  • Increase the spacing of cabling and reduce the parallel length of cabling. If necessary, Jog Out concave and convex cabling can be used.
  • Adding end matching can reduce reflection and reduce crosstalk;
  • Restrict the signal layer above the ground plane10milWithin range;
  • Insert a ground wire between the two lines with serious crosstalk for isolation to reduce crosstalk;
  • Avoid noise sources, such as MCU, inductance, crystal oscillator near the surface is strictly prohibited from wiring or drilling holes;

Copper clad

  • In PCB design, it is best to choose a larger grounding plane to cover the area without wiring, so as to provide shielding and improve decoupling ability;
  • Large copper foil should be avoided as far as possible around the heating element or in large current wiring, because long time heating will lead to copper foil expansion and fall off;
  • If a large area of copper foil must be used around the heating element, it is best to use grid copper coating to release the surface tension of the copper foil;
  • When the wiring distribution of the same layer is unbalanced or the copper distribution of different layers is asymmetrical, copper cladding is recommended.
  • If there is a large area in the outermost layer of PCB where there is no wiring, it is suggested to copper cover the grid in this area to make the overall copper foil distribution of PCB uniform;
  • It is recommended to lay between copper gridsBlank squaresThe size of theta is about theta25mil x 25mil;
  • Noise-sensitive circuits need to consider grounding shielding, that is, the width of the cloth around the signal layer is greater than50milGround or spacing less than300milThe hole;
  • Solitary copperExceeding (esp on the surface)150mils, do not drill a ground hole. You need to delete this area to avoid forming an aerial.

PCB makeup

Jigging refers to the processing method of V cutting or stamp hole processing for single PCB circuit board due to automatic SMT of electronic components. There are three common PCB collage methods: same direction collage, center symmetry collage, mirror symmetry collage.

Same direction board: the simplest board board way, the same type of PCB design tile copy can be realized.

Center symmetrical Mosaic: suitable for splicing two irregularly shaped PCB, the middle must be milling groove can be separated; If there is a large deformation after the Mosaic, you can consider adding an auxiliary block to the stamp hole connection in the Mosaic.

Mirror symmetry collage: Usually in the front side of PCB SMT components are able to satisfy the requirement of the reflow soldering welding was used, but should pay attention to the mirror symmetry puzzle need to meet the PCB light painting is negative symmetric distribution, such as the four layer board for power/ground layer 2 negative, is symmetrical layer 3 must also be negative, otherwise the puzzle cannot adopt the mirror symmetrical manner.

Process side

The process edge is an auxiliary part added to meet the needs of the automatic patch. It will be removed after production is completed and is generally designed to be 5mm.

  • Location hole: Used for positioning during PCB processing and testing, generally designed as2mm 的A hole;
  • Mark points: Used for automatic SMT machine identification and positioning, usually designed as1mm 的Welding plate;

Test point

Key components need test points on the PCB design to facilitate automated flying pin testing later. It is not allowed to use pads for welding patch components as test points. A separate and dedicated test pad must be designed to reduce the impact on spot detection and production commissioning. Pads used as test points should be distributed as far as possible on the same side of the PCB to reduce testing time and cost.

  • Test pointDistance to PCB edgeAs far as possible more than5mm;
  • Ensure that the test point is not covered by solder resistance layer or other ink;
  • The test point had better be tinned or sunk gold treatment to prevent oxidation;
  • Test points should be placed as far as possibleDistance element 1mmIn addition, avoid component by probe error impact;
  • Test point needsDistance locating hole The 3.2 mmThe above;
  • The test pointThe diameter ofNot less thanThe 0.4 mm, of the adjacent test pointspacingIn the bestThe 2.54 mmThe above;
  • Test surfaces cannot be placedhighlyMore thanThe 6.4 mmThe components to avoid the probe’s test fixture bumping into these high components;
  • To ensure that eachchipBoth have power and ground test points as close to the chip as possible (preferably less thanThe 2.54 mm);
  • When setting test points on PCB line, the width of test pad can be appropriately enlarged;
  • Test points should be evenly distributed on the PCB to avoid excessive stress concentration caused by probe pressure;
  • The power supply should be divided into areas with test points to facilitate decoupling and fault query;

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