Project open source address: github.com/Mculover666…

0. Tutorial complete directory

Before the migration, ensure that you are familiar with the uboot boot process. For details, see:

  • Uboot study notes | 02 – detailed exploration uboot start process (based on S3C2410 processor).

1. Create a board

  • ① Create a board directory and copy an existing directory (inBoard/Manufacturer modelBelow)

  • ② Create a board configuration file and copy it to the same fileInclude/configs/directory)

  • ③ Add the board configuration file

Modify the boards. CFG file in the root directory and add the board configuration file in the following format:

Target ARCH CPU Board name  Vendor SoC Options

// Target CPU architecture CPU architecture Board Name Vendor NAME SOC information
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Search smdk2410 and add a line 2440 like 24120:

At this point, all files of the new board are created, and the compilation test is completed:

make smdk2440_config
make
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If the configuration and compilation pass, it proves that the new board file is not a problem, then according to the Uboot boot process to modify the code.

2. Board configuration file

Section on adding the veneer of configuration files include/configs/smdk2440 h contains some of the most top macro definition configuration, need to constantly in the process of change.

  • Never change the top-level macro definition directly first!
  • Never change the top-level macro definition directly first!
  • Never change the top-level macro definition directly first!

3. Modify the initial configuration

In start_code, check for changes in turn.

Reference S3C2440 bare-metal article – 05 | S3C2440 clock system explanation (FCLK, PCLK, HCLK).

3.1. Modify the clock frequency division coefficient

#if defined(CONFIG_S3C2410)
	/* Self-added S3C2440 clock divider coefficient configuration */
	/* FCLK:HCLK:PCLK = =8:4:1 */
	/* default FCLK is 400 MHz ! * /
	ldr	r0, =CLKDIVN
	mov	r1, #5
	str	r1, [r0]

	/* HDIVN is not set to 0, set the CPU to asynchronous mode (source chip manual) */
	mrc p15,0,r0,c1,c0,0
	orr r0,r0,#0xc0000000  @#R1_nF:OR:R1_iA
	mcr p15,0,r0,c1,c0,0
#endif 
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3.2. Call lowlevel_init to set the memory controller

The SDRAM configuration of the memory controller is modified as follows:

TCHR option is removed from the address configuration, which is not found in S3C2440:

3.3. Modify board_init_f function

Set the stack top pointer sp in the board configuration file:



Therefore, skip to board_init_f without changing it.

In board_init_f function, board_early_init_f function needs to be modified, modify the clock configuration code:



As you can see, change the clock configuration by changing the values of M_MDIV, M_PDIV, M_SDIV, in this file:

USB is not currently used, so do not modify it.

3.4. Compile tests

make distclean
make smdk2440_config
make
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After compiling, use open-jtag to download the compiled u-boot.bin file to the nor Flash.

It takes 3-5 minutes to burn. You can first burn the normal Uboot into NOR Flash, and then download the uboot program through USB to send it to uboot through DNW tool.Store it in memory, this method is very fast download speed:



Then burn the program in memory to nor Flash:

Protect off All erase 0 7FFFF cp.b 30000000 0 80000 // Restart the development boardCopy the code

You can see that the uboot is running, but the serial port still has garbled characters, which indicates that the baud rate setting is wrong.

The normal uboot on Nor Flash has been destroyed and needs to be burned again.

4. Modify serial port Settings

Find the serial_init function in drivers/serial/serial_s3c24x0.c and find the serial_init_dev function in drivers/serial/serial_s3c24x0.c. The function ends with a jump to _serial_setbrg.

The _serial_setbrg function also calls get_PCLK in this file to calculate the value as follows:

	/* value is calculated so : (int)(PCLK/16./baudrate) -1 */
	reg = get_PCLK() / (16 * gd->baudrate) - 1;
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Check get_PCLK function, jump to file the arch/arm/CPU/arm920t/s3c24x0 / speed. C, you can see, the function calls the get_HCLK:

/* return PCLK frequency */
ulong get_PCLK(void)
{
	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();

	return (readl(&clk_power->clkdivn) & 1)? get_HCLK() /2 : get_HCLK();
}
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The get_HCLK function is also in this file, but the code is valid only if the macro CONFIG_S3C2440 is defined (the entire file also needs the macro CONFIG_S3C24X0 enabled) :

/* return HCLK frequency */
ulong get_HCLK(void)
{
	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
#ifdef CONFIG_S3C2440
	switch (readl(&clk_power->clkdivn) & 0x6) {
	default:
	case 0:
		return get_FCLK();
	case 2:
		return get_FCLK() / 2;
	case 4:
		return (readl(&clk_power->camdivn) & (1 << 9))? get_FCLK() /8 : get_FCLK() / 4;
	case 6:
		return (readl(&clk_power->camdivn) & (1 << 8))? get_FCLK() /6 : get_FCLK() / 3;
	}
#else
	return (readl(&clk_power->clkdivn) & 2)? get_FCLK() /2 : get_FCLK();
#endif
}
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5. Enable the CONFIG_S3C2440 macro definition

Enable this macro definition in the configuration file:

Then modify the code to configure the clock division coefficient in start.S:



After compiling, there is a problem with the NAND file. Here, do not use Nand flash for the moment, and shield related macro definitions in the board configuration file:

The yaffs2 file system is found to have a problem after compiling again. Here, the file system is not used for the moment, and relevant macro definitions are shielded in the board configuration file:

Recompile, no problem, download to the Nor Flash of the development board, check the serial port output, it can print normally, the initial port of uboot is successful:



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