A traveler asked the old monk, “What did you do before you attained enlightenment?” The old monk: “Chop wood and carry water for cooking.” The traveler asked, “What about the enlightenment?” The old monk: “Chop wood and carry water for cooking.” The traveler asked, “What is enlightenment then?” The old monk: “Before the Enlightenment, cutting wood thinking about carrying water, carrying water thinking about cooking; After the Enlightenment, chopping wood is chopping wood, carrying water is carrying water, cooking is cooking.”
Most of the time ordinary days are extraordinary.
Last time we talked about ARM V8’s anomalous direction scale (click here for the previous episode). Let’s take data Abort as an example. Assume that data abort occurs at the EL1 exception level. It jumps from the exception vector list to the assembly function el1_sync.
Kernel_entry on line 270 is an assembly macro that stores the location of the exception and stores the relevant CPU registers on the EL1 stack. Here, similar to ARM32 code, there will be a stack frame. The size of the stack frame is S_FRAME_SIZE, which is defined by software, not hardware. This means that you can implement a stack box that is different from the Linux implementation.
Next, read the value of the ESR_EL1j register. The ESR_EL1 register is called exception Syndrome Register. Refer to chapter D10.2.36 of the ARM V8 manual. This register is somewhat similar to the DFSR register in ARM V7. This register is defined in chapter D10.2.39.
In this register, the EC field holds the exception class. For data abort of the current EL, refer to the manual. EC== 100101 indicates that data abort occurs in the current EL.
The definition of the value and 273 lines of code ESR_ELx_EC_DABT_CUR is consistent, it defines in the arch/arm64 / include/asm/esr. H file.
So 274 lines of code will jump to the el1_da assembler function. This function is also in entry.s.
First, read the FAR_EL1 register. This register is in chapter D10.2.40. This register holds the virtual address that caused the exception to occur, and our operating system can read this register for subsequent exception handling. It is similar to the DFAR register in ARM V7.
The second step is to turn on the interrupt.
The third step is to abort do_mem_abort.
This function takes three arguments, of which the first and second arguments need to be noted. The first argument is the false virtual address of the FAR_EL1 register that was read when the exception occurred, and the second argument is the ESR_EL1 register. But the second parameter has a lot of glitches.
The ESR_EL1 register contains bits 26 to 31 that are Exception classes, and bits 0 to 24 that are ISS fields. ISS fields are coded differently. For this type of Data Abort, ISS is coded on page 2460 of the ARM V8 manual. See the diagram below.
Bits 0 to 5 indicate which type of data abort occurs. Let’s take the page table conversion error at Level 3 as an example (Translation Fault Level 3). We see that in DFSC domain, it is 000111, that is, number 7.
The arch/arm64/mm/fault.c file contains an array of fault_info[].
We were surprised to find that the number 7 in the fault_info[] array is translation fault for level 3. The corresponding handler is do_page_fault (line 386). You can count this array starting at 0.
We go through the ARM V8 anomaly through two episodes of stupid uncle go through the backstage, hope to help you. More exciting content please pay attention to the second season of Uncle Ben “Running Linux kernel” supporting video.
Season two is here
The video you’ve been waiting for for season 2 is here, and this time we’re going to do process management, lock mechanism, and interrupt management all in one. The flagship is still 1199, now 999 on sale.
First chapter: Understand the concepts of process management, locking and interrupt management thoroughly. Such as:
- The lifecycle of a process
- Process control block
- The nature of process scheduling
- The CFS scheduler
- How does progress switch work
- SMP Load balancing
- What is the size core scheduling
- Why interrupt
- The interrupt happens to what the ARMv7 and ARMv8 processors do
- Interrupts the underlying assembly processing
- Interrupt upper and lower half
- How to write an interrupt handler
- What about soft interrupts
- How to play Tasklets and workqueues
- What is an interrupt context
- Why locks are needed
- What is atomic operation
- How do ARMv7 and ARMv8 processors operate atomically
- What is the memory barrier
- How do you use the spinlock
- Semaphore and Mutex
- How do you use the RCU
- Why add a lock here
- .
The flagship article contains the content of the primary article and also contains the following features:
- Additional core code introduction, truly autonomous control.
- Comprehensive innovation experiment, uncle Ben led us to play a small OS on raspberry PI.
- Interview guide. Interview questions we’ve been abused over the years.
