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Bus timing refers to the control of time coordination between the two sides of the bus in the process of data exchange. This control is called bus timing, and its essence is a protocol or rule, which mainly has two basic timing modes: synchronous and asynchronous.
Bus operation and timing
Four phases of bus transmission
- Application allocation phase. Application is made by the master module (or master device) that needs to use the bus, and the bus arbitrator decides to grant the right to use the bus for the next transmission cycle to a certain applicant. This phase can also be subdivided into transport request and bus mediation phases.
- Application allocation phase. Application is made by the master module (or master device) that needs to use the bus, and the bus arbitrator decides to grant the right to use the bus for the next transmission cycle to a certain applicant. This phase can also be subdivided into transport request and bus mediation phases.
- Transport phase. Master module and slave module for data exchange, one-way or two-way data transmission. End phase. The information about the main module is removed from the system bus and the bus use right is given away.
Synchronous timing mode
- Unified clock
- The transmission speed is fast and the bus control logic is simple
- The validity test of data communication cannot be carried out in time and the reliability is poor
Asynchronous timing mode
- Timing control is achieved entirely by transmitting mutually restricted “handshake” signals
- The bus cycle length is variable to ensure reliable information exchange between two components and devices whose working speeds differ greatly
- Complex, slow
The asynchronous timing mode is divided into two types
- Do not interlock: the request is not back to withdraw, back to the request to withdraw
- Semi-interlock: request back to withdraw, back to request their own retreat
- Full interlock mode: the request is withdrawn only after it is returned, and the return is withdrawn after the request