1. Commonly used ARM instruction

1.1 Jump instruction

1. B: Unconditional forward

2. BL: jump instruction with connection

3. BX: unconditional jump with state switch

4. BLX: Unconditional jump with links and state switches

Such as:

B 0x1234Jump to absolute address0x1234Execute the corresponding code BL loc_234 to jump to the target LOC_234 address, this instruction is generally used between subroutines call BX R0 to jump to the R0 register specified address, and according to the lowest R0 to switch the processor stateCopy the code

1.2 Comparison Instructions

2. The register operates in the memory

2.1 Definition of register

Memory (main memory, memory)

Register data: can be a string, can be a number, can also be an address, can put various types of data.

Such as:

Address (e.g.,0x00004000) and the value that exists in the addressCopy the code

2.2 Common register instructions

– LDR: Load data from memory to register ← Load

Such as:

LDR R8,(R9,#4)
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R8 is the register for the data to be loaded, and the load value is the storage unit pointed to by R9+0x4.

1. Give the back to the front
2. Think of the whole thing inside the square brackets as the address

LDR R8,[R9,#4]
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R9+4, take the value in the address and assign it to R8

LDR R8,R9,#4
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Explanation: Assign the value of R9+4 to R8

– STR: stores register data to storage → Store

STR R8,[R9,#4] 
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Store the data in register R8 to the storage location pointed to by R9+0x4. (Place the value of R8 at the address of R9+4)

– LDM: loads memory data into a register list →

LDM R0, {r1-r3}Copy the code

Load the data of the storage unit pointed to by R0 into registers R1,R2,R3.

• STM: Store the data of a register list to the specified memory ←

• PUSH: to PUSH a register value onto the stack

• POP: push the stack value into the register (out of the stack)

• SWP: Data is exchanged between registers and memory

• SWP: Data is exchanged between registers and memory

SWP R1, R1 [R0]
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Swap register R1 with the contents of the storage unit pointed to by R0.

2.3 Data transmission instruction

• SMOV: Transfers data from the immediate count or register to the target register

MOV R0, #8  
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The R0 = 8

2.4 Data arithmetic operation instructions

ADD, SUB, the MUL, DIV please

Signed, unsigned operation, with carry operation.

2.5 Data logic operation instructions

• AND, AND

• Or: ORR

• Xor: EOR

• Logical Shift Left (LSL) : Logical Shift Left ←, the bit complement 0 Left at the lower end of the word in the register

• Logical Shift Right (LSR) : ← Logical Shift Right, the byte complement 0 left at the high end of the word in the register

• ASR (Arithmetic Shift Left) : Arithmetic right Shift, and the sign bit is kept unchanged in the displacement process, that is, if the source operand is positive, the bit Left empty at the high end of the word is filled with 0, otherwise 1 is filled

• ROR (Rotate Right) : circulates the left bits of the lower end of a word into the left bits of the upper end of a word

• Rotate Right eXtended by lplace RRX (Rotate Right eXtended by lplace) : The loop with the extension is rotated Right, the operands are rotated Right by one bit, and the left bits are filled with the original C flag value

Such as:

LSL R0, R1, #2
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The R0 = R1 * 4

2.6 Comparison Commands

• CMP: to compare the

CMP R0 #0 	
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The value in register R0 is compared to 0

Flag bits: such as z bits, which can be seen in the register window during dynamic debugging

2.7 Other Commands

• Coprocessor instruction: SWT (Switch user mode)
• Pseudoinstruction: DCB

2.8 Register addressing mode

• Immediate addressing: The address part after the opcode field in an immediate addressing instruction is the operand itself, that is, the data is contained in the instruction, and the fetch instruction retrieves the operand that can be used immediately (immediate number).

MOV R0,R0,#1
R0-1- > R0 MOV R0, #0xff00
0xff00- > R0Copy the code

• Register addressing: The value of the operand is in the register. The address field in the instruction indicates the register number. The instruction directly fetches the register value when it executes.

MOV R0,R1 R1- > R0 SUB R0,R1,R2 R1- > R0Copy the code

• Register offset addressing: The ARM instruction set is specific to addressing. When the second operand is register offset, the second register operand chooses to shift before combining with the first operand.

MOV R0,R1,LSL #2R2 shifted to the left2R0 is equal to R2 times4ANDS R1,R1,R2,LSL,R3 Shift the value of R2 to the left R3 bits, then phase with R1, and put the result into R1Copy the code

• Register indirection: The address code in the instruction gives a general register number, and the required operands are stored in the register address storage unit, that is, the register is the address pointer of the operands.

LDR R0,[R1] Take the value in R1 as the address, extract the data in this address and save it in R0 SWP R1,R1,[R2] Take the value in Ru as the address, and exchange the value in this address with the value in R1Copy the code

• Register indirect base offset addressing: an addressing method unique to the ARM instruction set. When the second operand is register offset, the second register operand chooses to shift before combining with the first operand.

LDR R0, [R1, # -4] sets the value of register R1 -0x4R0 MOV R0,R2,LSL, #3R2 shifted to the left33R0 is equal to R2 times8ANDS R1,R1,R2,LSL, R3 shift the value of R2 R3 bits to the left, then operate with R1, and put the result into R1Copy the code

• Base address: Add the contents of the base address register to the offset given in the instruction to form the effective address of the operand. Base address is used to access a storage location near the base address. It is often used for table lookup, array operations, feature register access, etc.

LDR R2,[R3,#0x0F] add the values in R30x0FSTR R1,[R0,#-2] subtract the value in R02As an address, save the contents of R1 to this address locationCopy the code

• Multi-register addressing: Several register values can be transmitted at a time, allowing an instruction to transmit any subset or all of the 16 registers.

LDMIA R1! ,{R2-r7,R12} read data from R1 cell to R2-R7,R12,R1 automatically add1STMIA R0! ,{r3-r6,R10} Save r3-r6,R10 data to the address pointed to by R0, R0 automatically add1
Copy the code

• Stack addressing: An area of storage that exits in a specific order. Operations can be “last in, first out” or “first in, last out.” Stack addressing is implicit in that it uses a special register (the stack pointer) to point to a storage area (the stack) and the location to which the pointer points is the top of the stack. Memory stacks can be divided into two types:
• Growing up: Growing to a high address, called an increasing stack
• Growing down: Growing to a lower address, called descending stack

The stack pointer points to the valid data item of the last stack pushed, called the full stack; The stack pointer points to the next empty location to be placed, called the empty stack. There are thus four types of stacks representing various combinations of increasing and decreasing full and empty stacks.

• Full increment: The stack grows upward by increasing the address of memory, and the stack pointer points to the highest address containing a valid item. Instructions such as LDMFA, STMFA, etc.
• Empty increment: The stack grows upward by increasing the address of memory, and the stack pointer points to the first empty location on the stack. Instructions such as LDMEA, STMEA and so on.
• Full decrement: The stack grows down by decreasing the address of memory, and the stack pointer points to the lowest address containing a valid item. Instructions such as LDMFD, STMFD and so on.
• Null decrement: The stack grows down by decreasing the address of memory, and the stack pointer points to the first empty location below the stack. Instructions such as LDMED, STMED, etc.

STMFD SP! ,{r1-r7,LR} push R1 to R7,LR. Full decrement stack. LDMFD SP! ,{r1-r7,LR} data out of the stack, into R1~R7,LR registers. Full decrement stack.Copy the code

The most obvious difference between ARM instruction and THUMB instruction is that the continuous address difference of 4 is ARM instruction, and the difference of 2 is THUMB instruction.