1. The MIPI sources

MIPI is an alliance established by ARM, TI and other companies in 2003, aiming to standardize various internal interfaces of mobile phones (camera CSI, display DSI, RF/baseband interface DigRF, etc.), so as to reduce the complexity of mobile phone design and increase the flexibility of design. Currently, mature interface applications include DSI(display interface). Both CSI(camera interface) and CSI(Camera interface) have relatively complex protocol structures. The figure below shows that a SOC can be used as a CSI receiver and also as a DSI output. D-phy is used in the physical layer, and the new physical layer c-PHY is also gradually adopted, as we often sayCamera I2CInterfaces have a special one in MIPICCI(Camera Control Interface)To the corresponding

2.MIPI Consortium display specification standards

  • DCS (Display Command Set)

Used to display the standardized command set in the command mode of the module;

  • DBI, DPI (Display Bus Interface, Display Pixel Interface)

DBI: Parallel interface with a display module with a display controller and frame buffer. DPI: Parallel interface with display module, without display controller or frame buffer.

  • DSI, CSI (Display Serial Interface, Camera Serial Interface)

DSI: high-speed serial interface between host processor and display module; CSI: high-speed serial interface between the host processor and the camera module;

  • D-PHY

Provide physical layer path definition for DSI and CSI;

2.1 the DSI/CSI stratification

CSI and DSI are layered pretty much the same

  • DCS Spec: Various algorithm modules for processing raw image data
  • DSI/CSI spec: perform data segmentation and reorganization, generate packet headers according to data types, and generate checksum sequences that constitute packet tails according to data contents. After that, the packet header, data itself and packet tail are combined, and the data is allocated to each channel reasonably. After that, the data is transferred to the physical layer (D-PHY) through digital-to-analog conversion. After receiving the data of the physical layer, the receiver unpacks the original data according to the previous reverse order
  • D-phy Spec: Generates the final MIPI waveform

3.MIPI D-PHY

3.1 D – PHY configuration

D – PHY need a clock channel and one or more data channels, all of the data channel needs to support high-speed data transmission and positive mode of Escape, data channel is divided into data channels of two types of two-way and one-way, including two-way to half note: two-way data channels should contain the following functions: (1) the HS reverse mode data transmission; (2) Escape mode reversed in LP mode;

Configuration options:1.One or more data channels;2.Two-way or unidirectional data channels on each channel;3.The type of back communication supported by each channel;4.Escape mode function on each direction of each channel;5.Data encoding mode; Raw or8b9 b code;Copy the code

3.2 D-PHY working mode

MIPI D-PHY clock works in a manner similar to DDR clock. Within a clock cycle,Data are collected from both rising and falling edges, has two working modes: High Speed (HS) and Low Power (LP). HS supports a maximum data transmission rate of 80Mbps to 4.5Gbps, and LP supports a maximum data transmission rate of 10Mbps. These two working modes work together. When the data is transmitted with a large amount of data, the data will be converted from LP mode to HS mode, and when the data is transmitted, the data will be converted from HS mode to LP mode to reduce power consumption. Generally, one pair of clock lane is matched with four pairs of data lane, where 10 PIN pins are required

  • HS high-speed transmission mode: used for transmitting burst data, synchronous transmission, differential signal, level range of 100MV-300mV, transmission speed range of 80m-1Gbps, in this mode of transmission, when the positive end of the difference line receives 300mV signal, when the negative end receives 100mV signal, at this time, the receiver identifies as 1, and vice versa

  • LP low power mode: used for transmission of control instructions, asynchronous transmission, single-end signal, level range of 0-1.2V, no clock line, clock is through two data lines or the speed is less than or equal to 10Mbps, in this mode of transmission, when the positive end receives 1.2V, the negative end receives 0V when the receiver is identified as 1, and vice versa

In HS mode, data and Clock lane are singly terminated with 50ohms resistor, and in LP mode, it is in high resistance state. When there is no data, BOTH D+ and D- work in the high level state of LP, which are single-ended signals. In HS mode, when high data transmission is required, it will go through a certain time sequenceFor each lane, the master terminal on the left needs hS-TX and LP-TX. These two modules are connected to the same data line corresponding to hS-RX and LP-RX on the slave terminal. The slave terminal needs an end resistor and LP-CD to check the status of LP.

4. Schematic diagram of d-PHY two modes

4.1 the HS model

In the following figure, the left side is the data transmitting end, that is, the master end, which has two structures similar to push pull. The right side is the differential signal receiving end, which is composed of two end resistors and end enable signals. The working mode is as follows: Difference of D + signals, for example, when the K2 and K4 opened, voltage through the line connected to the termination resistor, after termination can make open, two termination resistor forming circuit, this creates a differential signal is the change, when the K2 and K4 closed, form the change of the negative differential signal, D – controlled by K1 and K3, is a process instead

4.2 the LP model

Different from HS mode, RX terminal does not need to be terminated, which is infinite, and TX terminal only needs to be controlled to make corresponding changes. When LP high is needed to output 1.2V, only the above switch needs to be turned on, then D+ is 1.2V. When low power output needs to be controlled, the following switch needs to be turned on. In this way, the end voltage is low and the voltage changes are realized. Since D+ and D- are single-end signals in LP mode, D+ and D- can be controlled separately

5. Schematic diagram of data transmission in d-PHY three working modes

5.1 Clock Continuous Mode

Clock continuous mode is also calledHS-TXorI burst into tears.Mode, as can be seen from the figure, clock always exists and is in differential state. When there is no data transmission, data lane is in LP11 mode,D + and D- are both in high level state. When there is data transmission, it enters HS mode through a certain sequence, from LP01 to LP00, and then goes through THs-Zero state. After data transmission is completed, exit in accordance with a certain time sequenceEnter and exit the command as follows: Enter lP-11, LP-01, LP-00, SoT (00011101); Exit: EoT, LP11

5.2 Common Clock Mode

In the nomal mode of clock, when there is no data, clock lane is also in a high configuration, which makes clock lane also enter the low-power mode. Clock Lane enters the HS mode earlier than data lane. When data transmission is completed, Clock lane enters LP mode later than data lane, so clock lane is not continuous at this time

5.3 the Escape mode

Data can also be passed in LP mode, and this working state is calledEscape modeEnter the timing sequence as follows in LP modeThe timing of the red boxEscape mode, and then the corresponding data transmission, its clock is through D+ and D- xOR, mainly used for low-speed signal transmission, such as chip initialization workEnter: LP-11, LP-10, LP-00, LP-01, LP-00; Exit: LP10, LP11

6.MiPi multi-channel allocation and merger

For D-PHY, a clock data can support a maximum of four pairs of data lanes. The following shows data transmission on D-PHY in different lanes. The sender transmits data to the receiver through serial conversion in parallel, and the receiver parses data through reverse sequence

7. Other

MIPI is difference signals, anti-interference characteristics, anti-interference formula is: ((D +) + noise) – (-) (D – whose) = (D +) – (D)

More information can see MIPI official manual Source: note page.om.qq.com/page/OViWkv… www.bilibili.com/video/BV1Tv…